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target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M

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Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security
extensions are enabled.

We can freely add more items to vmstate_m_security without
breaking migration compatibility, because no CPU currently
has the ARM_FEATURE_M_SECURITY bit enabled and so this
subsection is not yet used by anything.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-14-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2017-09-07 13:54:53 +01:00
parent 4125e6feb7
commit 62c58ee0b2
5 changed files with 40 additions and 21 deletions
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8
hw/intc/armv7m_nvic.c
View file

@ -564,7 +564,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
if (region >= cpu->pmsav7_dregion) {
return 0;
}
return cpu->env.pmsav8.rbar[region];
return cpu->env.pmsav8.rbar[attrs.secure][region];
}
if (region >= cpu->pmsav7_dregion) {
@ -591,7 +591,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
if (region >= cpu->pmsav7_dregion) {
return 0;
}
return cpu->env.pmsav8.rlar[region];
return cpu->env.pmsav8.rlar[attrs.secure][region];
}
if (region >= cpu->pmsav7_dregion) {
@ -756,7 +756,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
if (region >= cpu->pmsav7_dregion) {
return;
}
cpu->env.pmsav8.rbar[region] = value;
cpu->env.pmsav8.rbar[attrs.secure][region] = value;
tlb_flush(CPU(cpu));
return;
}
@ -806,7 +806,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
if (region >= cpu->pmsav7_dregion) {
return;
}
cpu->env.pmsav8.rlar[region] = value;
cpu->env.pmsav8.rlar[attrs.secure][region] = value;
tlb_flush(CPU(cpu));
return;
}