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target/mips: Convert MSA MOVE.V opcode to decodetree

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Convert the MOVE.V opcode (Vector Move) to decodetree.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-28-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-10-19 18:26:03 +02:00
parent 97fe675519
commit 62ba0e855a
2 changed files with 20 additions and 6 deletions
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19
target/mips/tcg/msa_translate.c
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@ -46,7 +46,6 @@ enum {
/* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
OPC_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
};
static const char msaregnames[][6] = {
@ -533,6 +532,19 @@ TRANS_DF_iii_b(HADD_U, trans_msa_3r, gen_helper_msa_hadd_u);
TRANS_DF_iii_b(HSUB_S, trans_msa_3r, gen_helper_msa_hsub_s);
TRANS_DF_iii_b(HSUB_U, trans_msa_3r, gen_helper_msa_hsub_u);
static bool trans_MOVE_V(DisasContext *ctx, arg_msa_elm *a)
{
if (!check_msa_enabled(ctx)) {
return true;
}
gen_helper_msa_move_v(cpu_env,
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws));
return true;
}
static void gen_msa_elm_3e(DisasContext *ctx)
{
#define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
@ -551,9 +563,6 @@ static void gen_msa_elm_3e(DisasContext *ctx)
gen_helper_msa_cfcmsa(telm, cpu_env, tsr);
gen_store_gpr(telm, dest);
break;
case OPC_MOVE_V:
gen_helper_msa_move_v(cpu_env, tdt, tsr);
break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
@ -654,7 +663,7 @@ static void gen_msa_elm(DisasContext *ctx)
uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
if (dfn == 0x3E) {
/* CTCMSA, CFCMSA, MOVE.V */
/* CTCMSA, CFCMSA */
gen_msa_elm_3e(ctx);
return;
} else {