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util: Add cpuinfo-ppc.c

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Move the code from tcg/.  Fix a bug in that PPC_FEATURE2_ARCH_3_10
is actually spelled PPC_FEATURE2_ARCH_3_1.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-06-05 18:29:04 +03:00
parent 276d72ca1b
commit 623d7e3551
6 changed files with 97 additions and 51 deletions
Download patch file Download diff file Expand all files Collapse all files

44
tcg/ppc/tcg-target.c.inc
View file

@ -101,10 +101,7 @@
#define ALL_GENERAL_REGS 0xffffffffu
#define ALL_VECTOR_REGS 0xffffffff00000000ull
TCGPowerISA have_isa;
static bool have_isel;
bool have_altivec;
bool have_vsx;
#define have_isel (cpuinfo & CPUINFO_ISEL)
#ifndef CONFIG_SOFTMMU
#define TCG_GUEST_BASE_REG 30
@ -3879,45 +3876,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
static void tcg_target_init(TCGContext *s)
{
unsigned long hwcap = qemu_getauxval(AT_HWCAP);
unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2);
have_isa = tcg_isa_base;
if (hwcap & PPC_FEATURE_ARCH_2_06) {
have_isa = tcg_isa_2_06;
}
#ifdef PPC_FEATURE2_ARCH_2_07
if (hwcap2 & PPC_FEATURE2_ARCH_2_07) {
have_isa = tcg_isa_2_07;
}
#endif
#ifdef PPC_FEATURE2_ARCH_3_00
if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
have_isa = tcg_isa_3_00;
}
#endif
#ifdef PPC_FEATURE2_ARCH_3_10
if (hwcap2 & PPC_FEATURE2_ARCH_3_10) {
have_isa = tcg_isa_3_10;
}
#endif
#ifdef PPC_FEATURE2_HAS_ISEL
/* Prefer explicit instruction from the kernel. */
have_isel = (hwcap2 & PPC_FEATURE2_HAS_ISEL) != 0;
#else
/* Fall back to knowing Power7 (2.06) has ISEL. */
have_isel = have_isa_2_06;
#endif
if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
have_altivec = true;
/* We only care about the portion of VSX that overlaps Altivec. */
if (hwcap & PPC_FEATURE_HAS_VSX) {
have_vsx = true;
}
}
tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
if (have_altivec) {

16
tcg/ppc/tcg-target.h
View file

@ -25,6 +25,8 @@
#ifndef PPC_TCG_TARGET_H
#define PPC_TCG_TARGET_H
#include "host/cpuinfo.h"
#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
#define TCG_TARGET_NB_REGS 64
@ -61,14 +63,12 @@ typedef enum {
tcg_isa_3_10,
} TCGPowerISA;
extern TCGPowerISA have_isa;
extern bool have_altivec;
extern bool have_vsx;
#define have_isa_2_06 (have_isa >= tcg_isa_2_06)
#define have_isa_2_07 (have_isa >= tcg_isa_2_07)
#define have_isa_3_00 (have_isa >= tcg_isa_3_00)
#define have_isa_3_10 (have_isa >= tcg_isa_3_10)
#define have_isa_2_06 (cpuinfo & CPUINFO_V2_06)
#define have_isa_2_07 (cpuinfo & CPUINFO_V2_07)
#define have_isa_3_00 (cpuinfo & CPUINFO_V3_0)
#define have_isa_3_10 (cpuinfo & CPUINFO_V3_1)
#define have_altivec (cpuinfo & CPUINFO_ALTIVEC)
#define have_vsx (cpuinfo & CPUINFO_VSX)
/* optional instructions automatically implemented */
#define TCG_TARGET_HAS_ext8u_i32 0 /* andi */