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tcg: Merge INDEX_op_extract2_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
c8f9f70047
commit
61d6a8767a
6 changed files with 19 additions and 34 deletions
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@ -476,9 +476,9 @@ Misc
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| (using an arithmetic right shift) on TCG_TYPE_I32.
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* - extract2_i32/i64 *dest*, *t1*, *t2*, *pos*
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* - extract2 *dest*, *t1*, *t2*, *pos*
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- | For N = {32,64}, extract an N-bit quantity from the concatenation
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- | For TCG_TYPE_I{N}, extract an N-bit quantity from the concatenation
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of *t2*:*t1*, beginning at *pos*. The tcg_gen_extract2_{i32,i64} expander
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accepts 0 <= *pos* <= N as inputs. The backend code generator will
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not see either 0 or N as inputs for these opcodes.
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@ -56,6 +56,7 @@ DEF(divu, 1, 2, 0, TCG_OPF_INT)
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DEF(divu2, 2, 3, 0, TCG_OPF_INT)
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DEF(eqv, 1, 2, 0, TCG_OPF_INT)
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DEF(extract, 1, 1, 2, TCG_OPF_INT)
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DEF(extract2, 1, 2, 1, TCG_OPF_INT)
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DEF(movcond, 1, 4, 1, TCG_OPF_INT)
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DEF(mul, 1, 2, 0, TCG_OPF_INT)
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DEF(muls2, 2, 2, 0, TCG_OPF_INT)
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@ -90,8 +91,6 @@ DEF(ld_i32, 1, 1, 1, 0)
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DEF(st8_i32, 0, 2, 1, 0)
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DEF(st16_i32, 0, 2, 1, 0)
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DEF(st_i32, 0, 2, 1, 0)
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/* shifts/rotates */
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DEF(extract2_i32, 1, 2, 1, 0)
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DEF(add2_i32, 2, 4, 0, 0)
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DEF(sub2_i32, 2, 4, 0, 0)
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@ -110,8 +109,6 @@ DEF(st8_i64, 0, 2, 1, 0)
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DEF(st16_i64, 0, 2, 1, 0)
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DEF(st32_i64, 0, 2, 1, 0)
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DEF(st_i64, 0, 2, 1, 0)
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/* shifts/rotates */
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DEF(extract2_i64, 1, 2, 1, 0)
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/* size changing ops */
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DEF(ext_i32_i64, 1, 1, 0, 0)
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@ -19,16 +19,6 @@
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Sometimes, knowing what the backend has can produce better code.
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* The exact opcode to check depends on 32- vs. 64-bit.
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*/
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#ifdef TARGET_X86_64
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#define INDEX_op_extract2_tl INDEX_op_extract2_i64
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#else
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#define INDEX_op_extract2_tl INDEX_op_extract2_i32
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#endif
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#define MMX_OFFSET(reg) \
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({ assert((reg) >= 0 && (reg) <= 7); \
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offsetof(CPUX86State, fpregs[reg].mmx); })
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@ -3023,7 +3013,7 @@ static void gen_PMOVMSKB(DisasContext *s, X86DecodedInsn *decode)
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tcg_gen_ld8u_tl(s->T0, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1)));
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while (vec_len > 8) {
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vec_len -= 8;
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if (tcg_op_supported(INDEX_op_extract2_tl, TCG_TYPE_TL, 0)) {
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if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_TL, 0)) {
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/*
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* Load the next byte of the result into the high byte of T.
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* TCG does a similar expansion of deposit to shl+extract2; by
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@ -1873,12 +1873,12 @@ static bool fold_extract2(OptContext *ctx, TCGOp *op)
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uint64_t v2 = arg_info(op->args[2])->val;
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int shr = op->args[3];
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if (op->opc == INDEX_op_extract2_i64) {
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v1 >>= shr;
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v2 <<= 64 - shr;
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} else {
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if (ctx->type == TCG_TYPE_I32) {
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v1 = (uint32_t)v1 >> shr;
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v2 = (uint64_t)((int32_t)v2 << (32 - shr));
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} else {
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v1 >>= shr;
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v2 <<= 64 - shr;
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}
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return tcg_opt_gen_movi(ctx, op, op->args[0], v1 | v2);
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}
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@ -2878,7 +2878,7 @@ void tcg_optimize(TCGContext *s)
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case INDEX_op_extract:
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done = fold_extract(&ctx, op);
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break;
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CASE_OP_32_64(extract2):
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case INDEX_op_extract2:
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done = fold_extract2(&ctx, op);
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break;
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case INDEX_op_ext_i32_i64:
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16
tcg/tcg-op.c
16
tcg/tcg-op.c
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@ -921,7 +921,7 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
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t1 = tcg_temp_ebb_new_i32();
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if (tcg_op_supported(INDEX_op_extract2_i32, TCG_TYPE_I32, 0)) {
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if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_I32, 0)) {
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if (ofs + len == 32) {
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tcg_gen_shli_i32(t1, arg1, len);
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tcg_gen_extract2_i32(ret, t1, arg2, len);
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@ -1077,8 +1077,8 @@ void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
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tcg_gen_mov_i32(ret, ah);
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} else if (al == ah) {
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tcg_gen_rotri_i32(ret, al, ofs);
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} else if (tcg_op_supported(INDEX_op_extract2_i32, TCG_TYPE_I32, 0)) {
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tcg_gen_op4i_i32(INDEX_op_extract2_i32, ret, al, ah, ofs);
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} else if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_I32, 0)) {
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tcg_gen_op4i_i32(INDEX_op_extract2, ret, al, ah, ofs);
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} else {
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TCGv_i32 t0 = tcg_temp_ebb_new_i32();
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tcg_gen_shri_i32(t0, al, ofs);
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@ -1799,7 +1799,7 @@ static inline void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1,
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tcg_gen_movi_i32(TCGV_LOW(ret), 0);
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}
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} else if (right) {
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if (tcg_op_supported(INDEX_op_extract2_i32, TCG_TYPE_I32, 0)) {
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if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_I32, 0)) {
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tcg_gen_extract2_i32(TCGV_LOW(ret),
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TCGV_LOW(arg1), TCGV_HIGH(arg1), c);
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} else {
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@ -1813,7 +1813,7 @@ static inline void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1,
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tcg_gen_shri_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
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}
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} else {
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if (tcg_op_supported(INDEX_op_extract2_i32, TCG_TYPE_I32, 0)) {
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if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_I32, 0)) {
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tcg_gen_extract2_i32(TCGV_HIGH(ret),
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TCGV_LOW(arg1), TCGV_HIGH(arg1), 32 - c);
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} else {
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@ -2553,7 +2553,7 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
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t1 = tcg_temp_ebb_new_i64();
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if (tcg_op_supported(INDEX_op_extract2_i64, TCG_TYPE_I64, 0)) {
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if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_I64, 0)) {
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if (ofs + len == 64) {
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tcg_gen_shli_i64(t1, arg1, len);
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tcg_gen_extract2_i64(ret, t1, arg2, len);
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@ -2781,8 +2781,8 @@ void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
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tcg_gen_mov_i64(ret, ah);
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} else if (al == ah) {
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tcg_gen_rotri_i64(ret, al, ofs);
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} else if (tcg_op_supported(INDEX_op_extract2_i64, TCG_TYPE_I64, 0)) {
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tcg_gen_op4i_i64(INDEX_op_extract2_i64, ret, al, ah, ofs);
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} else if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_I64, 0)) {
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tcg_gen_op4i_i64(INDEX_op_extract2, ret, al, ah, ofs);
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} else {
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TCGv_i64 t0 = tcg_temp_ebb_new_i64();
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tcg_gen_shri_i64(t0, al, ofs);
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@ -1146,8 +1146,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
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OUTOP(INDEX_op_divu2, TCGOutOpDivRem, outop_divu2),
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OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv),
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OUTOP(INDEX_op_extract, TCGOutOpExtract, outop_extract),
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OUTOP(INDEX_op_extract2_i32, TCGOutOpExtract2, outop_extract2),
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OUTOP(INDEX_op_extract2_i64, TCGOutOpExtract2, outop_extract2),
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OUTOP(INDEX_op_extract2, TCGOutOpExtract2, outop_extract2),
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OUTOP(INDEX_op_movcond, TCGOutOpMovcond, outop_movcond),
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OUTOP(INDEX_op_mul, TCGOutOpBinary, outop_mul),
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OUTOP(INDEX_op_muls2, TCGOutOpMul2, outop_muls2),
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@ -5597,8 +5596,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
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}
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break;
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case INDEX_op_extract2_i32:
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case INDEX_op_extract2_i64:
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case INDEX_op_extract2:
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{
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const TCGOutOpExtract2 *out = &outop_extract2;
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