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ppc4xx_sdram: Rename local state variable for brevity

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Rename the sdram local state variable to s in dcr read/write functions
and reset methods for better readability and to match realize methods.
Other places not converted will be changed or removed in subsequent
patches.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <8e7539cb1fccd7556b68351c4dcf62534c3a69cf.1666194485.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
BALATON Zoltan 2022-10-19 18:02:56 +02:00 • committed by Daniel Henrique Barboza
parent c8c6d68af7
commit 61cfe0df90
1 changed files with 78 additions and 78 deletions
Download patch file Download diff file Expand all files Collapse all files

156
hw/ppc/ppc4xx_sdram.c
View file

@ -237,56 +237,56 @@ static void sdram_ddr_unmap_bcr(Ppc4xxSdramDdrState *sdram)
static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn) static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
{ {
Ppc4xxSdramDdrState *sdram = opaque; Ppc4xxSdramDdrState *s = opaque;
uint32_t ret; uint32_t ret;
switch (dcrn) { switch (dcrn) {
case SDRAM0_CFGADDR: case SDRAM0_CFGADDR:
ret = sdram->addr; ret = s->addr;
break; break;
case SDRAM0_CFGDATA: case SDRAM0_CFGDATA:
switch (sdram->addr) { switch (s->addr) {
case 0x00: /* SDRAM_BESR0 */ case 0x00: /* SDRAM_BESR0 */
ret = sdram->besr0; ret = s->besr0;
break; break;
case 0x08: /* SDRAM_BESR1 */ case 0x08: /* SDRAM_BESR1 */
ret = sdram->besr1; ret = s->besr1;
break; break;
case 0x10: /* SDRAM_BEAR */ case 0x10: /* SDRAM_BEAR */
ret = sdram->bear; ret = s->bear;
break; break;
case 0x20: /* SDRAM_CFG */ case 0x20: /* SDRAM_CFG */
ret = sdram->cfg; ret = s->cfg;
break; break;
case 0x24: /* SDRAM_STATUS */ case 0x24: /* SDRAM_STATUS */
ret = sdram->status; ret = s->status;
break; break;
case 0x30: /* SDRAM_RTR */ case 0x30: /* SDRAM_RTR */
ret = sdram->rtr; ret = s->rtr;
break; break;
case 0x34: /* SDRAM_PMIT */ case 0x34: /* SDRAM_PMIT */
ret = sdram->pmit; ret = s->pmit;
break; break;
case 0x40: /* SDRAM_B0CR */ case 0x40: /* SDRAM_B0CR */
ret = sdram->bank[0].bcr; ret = s->bank[0].bcr;
break; break;
case 0x44: /* SDRAM_B1CR */ case 0x44: /* SDRAM_B1CR */
ret = sdram->bank[1].bcr; ret = s->bank[1].bcr;
break; break;
case 0x48: /* SDRAM_B2CR */ case 0x48: /* SDRAM_B2CR */
ret = sdram->bank[2].bcr; ret = s->bank[2].bcr;
break; break;
case 0x4C: /* SDRAM_B3CR */ case 0x4C: /* SDRAM_B3CR */
ret = sdram->bank[3].bcr; ret = s->bank[3].bcr;
break; break;
case 0x80: /* SDRAM_TR */ case 0x80: /* SDRAM_TR */
ret = -1; /* ? */ ret = -1; /* ? */
break; break;
case 0x94: /* SDRAM_ECCCFG */ case 0x94: /* SDRAM_ECCCFG */
ret = sdram->ecccfg; ret = s->ecccfg;
break; break;
case 0x98: /* SDRAM_ECCESR */ case 0x98: /* SDRAM_ECCESR */
ret = sdram->eccesr; ret = s->eccesr;
break; break;
default: /* Error */ default: /* Error */
ret = -1; ret = -1;
@ -304,78 +304,78 @@ static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val) static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
{ {
Ppc4xxSdramDdrState *sdram = opaque; Ppc4xxSdramDdrState *s = opaque;
switch (dcrn) { switch (dcrn) {
case SDRAM0_CFGADDR: case SDRAM0_CFGADDR:
sdram->addr = val; s->addr = val;
break; break;
case SDRAM0_CFGDATA: case SDRAM0_CFGDATA:
switch (sdram->addr) { switch (s->addr) {
case 0x00: /* SDRAM_BESR0 */ case 0x00: /* SDRAM_BESR0 */
sdram->besr0 &= ~val; s->besr0 &= ~val;
break; break;
case 0x08: /* SDRAM_BESR1 */ case 0x08: /* SDRAM_BESR1 */
sdram->besr1 &= ~val; s->besr1 &= ~val;
break; break;
case 0x10: /* SDRAM_BEAR */ case 0x10: /* SDRAM_BEAR */
sdram->bear = val; s->bear = val;
break; break;
case 0x20: /* SDRAM_CFG */ case 0x20: /* SDRAM_CFG */
val &= 0xFFE00000; val &= 0xFFE00000;
if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) { if (!(s->cfg & 0x80000000) && (val & 0x80000000)) {
trace_ppc4xx_sdram_enable("enable"); trace_ppc4xx_sdram_enable("enable");
/* validate all RAM mappings */ /* validate all RAM mappings */
sdram_ddr_map_bcr(sdram); sdram_ddr_map_bcr(s);
sdram->status &= ~0x80000000; s->status &= ~0x80000000;
} else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) { } else if ((s->cfg & 0x80000000) && !(val & 0x80000000)) {
trace_ppc4xx_sdram_enable("disable"); trace_ppc4xx_sdram_enable("disable");
/* invalidate all RAM mappings */ /* invalidate all RAM mappings */
sdram_ddr_unmap_bcr(sdram); sdram_ddr_unmap_bcr(s);
sdram->status |= 0x80000000; s->status |= 0x80000000;
} }
if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) { if (!(s->cfg & 0x40000000) && (val & 0x40000000)) {
sdram->status |= 0x40000000; s->status |= 0x40000000;
} else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) { } else if ((s->cfg & 0x40000000) && !(val & 0x40000000)) {
sdram->status &= ~0x40000000; s->status &= ~0x40000000;
} }
sdram->cfg = val; s->cfg = val;
break; break;
case 0x24: /* SDRAM_STATUS */ case 0x24: /* SDRAM_STATUS */
/* Read-only register */ /* Read-only register */
break; break;
case 0x30: /* SDRAM_RTR */ case 0x30: /* SDRAM_RTR */
sdram->rtr = val & 0x3FF80000; s->rtr = val & 0x3FF80000;
break; break;
case 0x34: /* SDRAM_PMIT */ case 0x34: /* SDRAM_PMIT */
sdram->pmit = (val & 0xF8000000) | 0x07C00000; s->pmit = (val & 0xF8000000) | 0x07C00000;
break; break;
case 0x40: /* SDRAM_B0CR */ case 0x40: /* SDRAM_B0CR */
sdram_ddr_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000); sdram_ddr_set_bcr(s, 0, val, s->cfg & 0x80000000);
break; break;
case 0x44: /* SDRAM_B1CR */ case 0x44: /* SDRAM_B1CR */
sdram_ddr_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000); sdram_ddr_set_bcr(s, 1, val, s->cfg & 0x80000000);
break; break;
case 0x48: /* SDRAM_B2CR */ case 0x48: /* SDRAM_B2CR */
sdram_ddr_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000); sdram_ddr_set_bcr(s, 2, val, s->cfg & 0x80000000);
break; break;
case 0x4C: /* SDRAM_B3CR */ case 0x4C: /* SDRAM_B3CR */
sdram_ddr_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000); sdram_ddr_set_bcr(s, 3, val, s->cfg & 0x80000000);
break; break;
case 0x80: /* SDRAM_TR */ case 0x80: /* SDRAM_TR */
sdram->tr = val & 0x018FC01F; s->tr = val & 0x018FC01F;
break; break;
case 0x94: /* SDRAM_ECCCFG */ case 0x94: /* SDRAM_ECCCFG */
sdram->ecccfg = val & 0x00F00000; s->ecccfg = val & 0x00F00000;
break; break;
case 0x98: /* SDRAM_ECCESR */ case 0x98: /* SDRAM_ECCESR */
val &= 0xFFF0F000; val &= 0xFFF0F000;
if (sdram->eccesr == 0 && val != 0) { if (s->eccesr == 0 && val != 0) {
qemu_irq_raise(sdram->irq); qemu_irq_raise(s->irq);
} else if (sdram->eccesr != 0 && val == 0) { } else if (s->eccesr != 0 && val == 0) {
qemu_irq_lower(sdram->irq); qemu_irq_lower(s->irq);
} }
sdram->eccesr = val; s->eccesr = val;
break; break;
default: /* Error */ default: /* Error */
break; break;
@ -386,21 +386,21 @@ static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
static void ppc4xx_sdram_ddr_reset(DeviceState *dev) static void ppc4xx_sdram_ddr_reset(DeviceState *dev)
{ {
Ppc4xxSdramDdrState *sdram = PPC4xx_SDRAM_DDR(dev); Ppc4xxSdramDdrState *s = PPC4xx_SDRAM_DDR(dev);
sdram->addr = 0; s->addr = 0;
sdram->bear = 0; s->bear = 0;
sdram->besr0 = 0; /* No error */ s->besr0 = 0; /* No error */
sdram->besr1 = 0; /* No error */ s->besr1 = 0; /* No error */
sdram->cfg = 0; s->cfg = 0;
sdram->ecccfg = 0; /* No ECC */ s->ecccfg = 0; /* No ECC */
sdram->eccesr = 0; /* No error */ s->eccesr = 0; /* No error */
sdram->pmit = 0x07C00000; s->pmit = 0x07C00000;
sdram->rtr = 0x05F00000; s->rtr = 0x05F00000;
sdram->tr = 0x00854009; s->tr = 0x00854009;
/* We pre-initialize RAM banks */ /* We pre-initialize RAM banks */
sdram->status = 0; s->status = 0;
sdram->cfg = 0x00800000; s->cfg = 0x00800000;
} }
static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp) static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp)
@ -572,7 +572,7 @@ static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *sdram)
static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn) static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
{ {
Ppc4xxSdramDdr2State *sdram = opaque; Ppc4xxSdramDdr2State *s = opaque;
uint32_t ret = 0; uint32_t ret = 0;
switch (dcrn) { switch (dcrn) {
@ -580,9 +580,9 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
case SDRAM_R1BAS: case SDRAM_R1BAS:
case SDRAM_R2BAS: case SDRAM_R2BAS:
case SDRAM_R3BAS: case SDRAM_R3BAS:
if (sdram->bank[dcrn - SDRAM_R0BAS].size) { if (s->bank[dcrn - SDRAM_R0BAS].size) {
ret = sdram_ddr2_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base, ret = sdram_ddr2_bcr(s->bank[dcrn - SDRAM_R0BAS].base,
sdram->bank[dcrn - SDRAM_R0BAS].size); s->bank[dcrn - SDRAM_R0BAS].size);
} }
break; break;
case SDRAM_CONF1HB: case SDRAM_CONF1HB:
@ -592,16 +592,16 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
case SDRAM_PLBADDUHB: case SDRAM_PLBADDUHB:
break; break;
case SDRAM0_CFGADDR: case SDRAM0_CFGADDR:
ret = sdram->addr; ret = s->addr;
break; break;
case SDRAM0_CFGDATA: case SDRAM0_CFGDATA:
switch (sdram->addr) { switch (s->addr) {
case 0x14: /* SDRAM_MCSTAT (405EX) */ case 0x14: /* SDRAM_MCSTAT (405EX) */
case 0x1F: case 0x1F:
ret = 0x80000000; ret = 0x80000000;
break; break;
case 0x21: /* SDRAM_MCOPT2 */ case 0x21: /* SDRAM_MCOPT2 */
ret = sdram->mcopt2; ret = s->mcopt2;
break; break;
case 0x40: /* SDRAM_MB0CF */ case 0x40: /* SDRAM_MB0CF */
ret = 0x00008001; ret = 0x00008001;
@ -627,7 +627,7 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val) static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
{ {
Ppc4xxSdramDdr2State *sdram = opaque; Ppc4xxSdramDdr2State *s = opaque;
switch (dcrn) { switch (dcrn) {
case SDRAM_R0BAS: case SDRAM_R0BAS:
@ -641,25 +641,25 @@ static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
case SDRAM_PLBADDUHB: case SDRAM_PLBADDUHB:
break; break;
case SDRAM0_CFGADDR: case SDRAM0_CFGADDR:
sdram->addr = val; s->addr = val;
break; break;
case SDRAM0_CFGDATA: case SDRAM0_CFGDATA:
switch (sdram->addr) { switch (s->addr) {
case 0x00: /* B0CR */ case 0x00: /* B0CR */
break; break;
case 0x21: /* SDRAM_MCOPT2 */ case 0x21: /* SDRAM_MCOPT2 */
if (!(sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) && if (!(s->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
(val & SDRAM_DDR2_MCOPT2_DCEN)) { (val & SDRAM_DDR2_MCOPT2_DCEN)) {
trace_ppc4xx_sdram_enable("enable"); trace_ppc4xx_sdram_enable("enable");
/* validate all RAM mappings */ /* validate all RAM mappings */
sdram_ddr2_map_bcr(sdram); sdram_ddr2_map_bcr(s);
sdram->mcopt2 |= SDRAM_DDR2_MCOPT2_DCEN; s->mcopt2 |= SDRAM_DDR2_MCOPT2_DCEN;
} else if ((sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) && } else if ((s->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
!(val & SDRAM_DDR2_MCOPT2_DCEN)) { !(val & SDRAM_DDR2_MCOPT2_DCEN)) {
trace_ppc4xx_sdram_enable("disable"); trace_ppc4xx_sdram_enable("disable");
/* invalidate all RAM mappings */ /* invalidate all RAM mappings */
sdram_ddr2_unmap_bcr(sdram); sdram_ddr2_unmap_bcr(s);
sdram->mcopt2 &= ~SDRAM_DDR2_MCOPT2_DCEN; s->mcopt2 &= ~SDRAM_DDR2_MCOPT2_DCEN;
} }
break; break;
default: default:
@ -673,10 +673,10 @@ static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
static void ppc4xx_sdram_ddr2_reset(DeviceState *dev) static void ppc4xx_sdram_ddr2_reset(DeviceState *dev)
{ {
Ppc4xxSdramDdr2State *sdram = PPC4xx_SDRAM_DDR2(dev); Ppc4xxSdramDdr2State *s = PPC4xx_SDRAM_DDR2(dev);
sdram->addr = 0; s->addr = 0;
sdram->mcopt2 = 0; s->mcopt2 = 0;
} }
static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp) static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp)