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tcg/i386: Introduce HostAddress

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Collect the 4 potential parts of the host address into a struct.
Reorg tcg_out_qemu_{ld,st}_direct to use it.
Reorg guest_base handling to use it.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-04-19 18:29:14 +02:00
parent 3174941fe0
commit 61713c29a9
1 changed files with 90 additions and 75 deletions
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165
tcg/i386/tcg-target.c.inc
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@ -1751,6 +1751,13 @@ static void tcg_out_nopn(TCGContext *s, int n)
tcg_out8(s, 0x90); tcg_out8(s, 0x90);
} }
typedef struct {
TCGReg base;
int index;
int ofs;
int seg;
} HostAddress;
#if defined(CONFIG_SOFTMMU) #if defined(CONFIG_SOFTMMU)
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra) * int mmu_idx, uintptr_t ra)
@ -2113,17 +2120,13 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
return tcg_out_fail_alignment(s, l); return tcg_out_fail_alignment(s, l);
} }
#if TCG_TARGET_REG_BITS == 32 static HostAddress x86_guest_base = {
# define x86_guest_base_seg 0 .index = -1
# define x86_guest_base_index -1 };
# define x86_guest_base_offset guest_base
#else #if defined(__x86_64__) && defined(__linux__)
static int x86_guest_base_seg; # include <asm/prctl.h>
static int x86_guest_base_index = -1; # include <sys/prctl.h>
static int32_t x86_guest_base_offset;
# if defined(__x86_64__) && defined(__linux__)
# include <asm/prctl.h>
# include <sys/prctl.h>
int arch_prctl(int code, unsigned long addr); int arch_prctl(int code, unsigned long addr);
static inline int setup_guest_base_seg(void) static inline int setup_guest_base_seg(void)
{ {
@ -2132,8 +2135,9 @@ static inline int setup_guest_base_seg(void)
} }
return 0; return 0;
} }
# elif defined (__FreeBSD__) || defined (__FreeBSD_kernel__) #elif defined(__x86_64__) && \
# include <machine/sysarch.h> (defined (__FreeBSD__) || defined (__FreeBSD_kernel__))
# include <machine/sysarch.h>
static inline int setup_guest_base_seg(void) static inline int setup_guest_base_seg(void)
{ {
if (sysarch(AMD64_SET_GSBASE, &guest_base) == 0) { if (sysarch(AMD64_SET_GSBASE, &guest_base) == 0) {
@ -2141,18 +2145,16 @@ static inline int setup_guest_base_seg(void)
} }
return 0; return 0;
} }
# else #else
static inline int setup_guest_base_seg(void) static inline int setup_guest_base_seg(void)
{ {
return 0; return 0;
} }
# endif #endif /* setup_guest_base_seg */
#endif
#endif /* SOFTMMU */ #endif /* SOFTMMU */
static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
TCGReg base, int index, intptr_t ofs, HostAddress h, TCGType type, MemOp memop)
int seg, TCGType type, MemOp memop)
{ {
bool use_movbe = false; bool use_movbe = false;
int rexw = (type == TCG_TYPE_I32 ? 0 : P_REXW); int rexw = (type == TCG_TYPE_I32 ? 0 : P_REXW);
@ -2167,60 +2169,61 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
switch (memop & MO_SSIZE) { switch (memop & MO_SSIZE) {
case MO_UB: case MO_UB:
tcg_out_modrm_sib_offset(s, OPC_MOVZBL + seg, datalo, tcg_out_modrm_sib_offset(s, OPC_MOVZBL + h.seg, datalo,
base, index, 0, ofs); h.base, h.index, 0, h.ofs);
break; break;
case MO_SB: case MO_SB:
tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + seg, datalo, tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + h.seg, datalo,
base, index, 0, ofs); h.base, h.index, 0, h.ofs);
break; break;
case MO_UW: case MO_UW:
if (use_movbe) { if (use_movbe) {
/* There is no extending movbe; only low 16-bits are modified. */ /* There is no extending movbe; only low 16-bits are modified. */
if (datalo != base && datalo != index) { if (datalo != h.base && datalo != h.index) {
/* XOR breaks dependency chains. */ /* XOR breaks dependency chains. */
tgen_arithr(s, ARITH_XOR, datalo, datalo); tgen_arithr(s, ARITH_XOR, datalo, datalo);
tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.seg,
datalo, base, index, 0, ofs); datalo, h.base, h.index, 0, h.ofs);
} else { } else {
tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.seg,
datalo, base, index, 0, ofs); datalo, h.base, h.index, 0, h.ofs);
tcg_out_ext16u(s, datalo, datalo); tcg_out_ext16u(s, datalo, datalo);
} }
} else { } else {
tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, tcg_out_modrm_sib_offset(s, OPC_MOVZWL + h.seg, datalo,
base, index, 0, ofs); h.base, h.index, 0, h.ofs);
} }
break; break;
case MO_SW: case MO_SW:
if (use_movbe) { if (use_movbe) {
tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.seg,
datalo, base, index, 0, ofs); datalo, h.base, h.index, 0, h.ofs);
tcg_out_ext16s(s, type, datalo, datalo); tcg_out_ext16s(s, type, datalo, datalo);
} else { } else {
tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + seg, tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + h.seg,
datalo, base, index, 0, ofs); datalo, h.base, h.index, 0, h.ofs);
} }
break; break;
case MO_UL: case MO_UL:
tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); tcg_out_modrm_sib_offset(s, movop + h.seg, datalo,
h.base, h.index, 0, h.ofs);
break; break;
#if TCG_TARGET_REG_BITS == 64 #if TCG_TARGET_REG_BITS == 64
case MO_SL: case MO_SL:
if (use_movbe) { if (use_movbe) {
tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + seg, datalo, tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + h.seg, datalo,
base, index, 0, ofs); h.base, h.index, 0, h.ofs);
tcg_out_ext32s(s, datalo, datalo); tcg_out_ext32s(s, datalo, datalo);
} else { } else {
tcg_out_modrm_sib_offset(s, OPC_MOVSLQ + seg, datalo, tcg_out_modrm_sib_offset(s, OPC_MOVSLQ + h.seg, datalo,
base, index, 0, ofs); h.base, h.index, 0, h.ofs);
} }
break; break;
#endif #endif
case MO_UQ: case MO_UQ:
if (TCG_TARGET_REG_BITS == 64) { if (TCG_TARGET_REG_BITS == 64) {
tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo,
base, index, 0, ofs); h.base, h.index, 0, h.ofs);
break; break;
} }
if (use_movbe) { if (use_movbe) {
@ -2228,15 +2231,16 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
datalo = datahi; datalo = datahi;
datahi = t; datahi = t;
} }
if (base == datalo || index == datalo) { if (h.base == datalo || h.index == datalo) {
tcg_out_modrm_sib_offset(s, OPC_LEA, datahi, base, index, 0, ofs); tcg_out_modrm_sib_offset(s, OPC_LEA, datahi,
tcg_out_modrm_offset(s, movop + seg, datalo, datahi, 0); h.base, h.index, 0, h.ofs);
tcg_out_modrm_offset(s, movop + seg, datahi, datahi, 4); tcg_out_modrm_offset(s, movop + h.seg, datalo, datahi, 0);
tcg_out_modrm_offset(s, movop + h.seg, datahi, datahi, 4);
} else { } else {
tcg_out_modrm_sib_offset(s, movop + seg, datalo, tcg_out_modrm_sib_offset(s, movop + h.seg, datalo,
base, index, 0, ofs); h.base, h.index, 0, h.ofs);
tcg_out_modrm_sib_offset(s, movop + seg, datahi, tcg_out_modrm_sib_offset(s, movop + h.seg, datahi,
base, index, 0, ofs + 4); h.base, h.index, 0, h.ofs + 4);
} }
break; break;
default: default:
@ -2249,6 +2253,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
MemOpIdx oi, TCGType data_type) MemOpIdx oi, TCGType data_type)
{ {
MemOp opc = get_memop(oi); MemOp opc = get_memop(oi);
HostAddress h;
#if defined(CONFIG_SOFTMMU) #if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[2]; tcg_insn_unit *label_ptr[2];
@ -2257,8 +2262,11 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
label_ptr, offsetof(CPUTLBEntry, addr_read)); label_ptr, offsetof(CPUTLBEntry, addr_read));
/* TLB Hit. */ /* TLB Hit. */
tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, h.base = TCG_REG_L1;
-1, 0, 0, data_type, opc); h.index = -1;
h.ofs = 0;
h.seg = 0;
tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, opc);
/* Record the current context of a load into ldst label */ /* Record the current context of a load into ldst label */
add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi, add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi,
@ -2269,15 +2277,14 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
} }
tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index, h = x86_guest_base;
x86_guest_base_offset, x86_guest_base_seg, h.base = addrlo;
data_type, opc); tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, opc);
#endif #endif
} }
static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
TCGReg base, int index, intptr_t ofs, HostAddress h, MemOp memop)
int seg, MemOp memop)
{ {
bool use_movbe = false; bool use_movbe = false;
int movop = OPC_MOVL_EvGv; int movop = OPC_MOVL_EvGv;
@ -2296,30 +2303,31 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
case MO_8: case MO_8:
/* This is handled with constraints on INDEX_op_qemu_st8_i32. */ /* This is handled with constraints on INDEX_op_qemu_st8_i32. */
tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || datalo < 4); tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || datalo < 4);
tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg, tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + h.seg,
datalo, base, index, 0, ofs); datalo, h.base, h.index, 0, h.ofs);
break; break;
case MO_16: case MO_16:
tcg_out_modrm_sib_offset(s, movop + P_DATA16 + seg, datalo, tcg_out_modrm_sib_offset(s, movop + P_DATA16 + h.seg, datalo,
base, index, 0, ofs); h.base, h.index, 0, h.ofs);
break; break;
case MO_32: case MO_32:
tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); tcg_out_modrm_sib_offset(s, movop + h.seg, datalo,
h.base, h.index, 0, h.ofs);
break; break;
case MO_64: case MO_64:
if (TCG_TARGET_REG_BITS == 64) { if (TCG_TARGET_REG_BITS == 64) {
tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo,
base, index, 0, ofs); h.base, h.index, 0, h.ofs);
} else { } else {
if (use_movbe) { if (use_movbe) {
TCGReg t = datalo; TCGReg t = datalo;
datalo = datahi; datalo = datahi;
datahi = t; datahi = t;
} }
tcg_out_modrm_sib_offset(s, movop + seg, datalo, tcg_out_modrm_sib_offset(s, movop + h.seg, datalo,
base, index, 0, ofs); h.base, h.index, 0, h.ofs);
tcg_out_modrm_sib_offset(s, movop + seg, datahi, tcg_out_modrm_sib_offset(s, movop + h.seg, datahi,
base, index, 0, ofs + 4); h.base, h.index, 0, h.ofs + 4);
} }
break; break;
default: default:
@ -2332,6 +2340,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
MemOpIdx oi, TCGType data_type) MemOpIdx oi, TCGType data_type)
{ {
MemOp opc = get_memop(oi); MemOp opc = get_memop(oi);
HostAddress h;
#if defined(CONFIG_SOFTMMU) #if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[2]; tcg_insn_unit *label_ptr[2];
@ -2340,7 +2349,11 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
label_ptr, offsetof(CPUTLBEntry, addr_write)); label_ptr, offsetof(CPUTLBEntry, addr_write));
/* TLB Hit. */ /* TLB Hit. */
tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc); h.base = TCG_REG_L1;
h.index = -1;
h.ofs = 0;
h.seg = 0;
tcg_out_qemu_st_direct(s, datalo, datahi, h, opc);
/* Record the current context of a store into ldst label */ /* Record the current context of a store into ldst label */
add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi, add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi,
@ -2351,8 +2364,10 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits);
} }
tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, x86_guest_base_index, h = x86_guest_base;
x86_guest_base_offset, x86_guest_base_seg, opc); h.base = addrlo;
tcg_out_qemu_st_direct(s, datalo, datahi, h, opc);
#endif #endif
} }
@ -4058,18 +4073,18 @@ static void tcg_target_qemu_prologue(TCGContext *s)
(ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4 (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4
+ stack_addend); + stack_addend);
#else #else
# if !defined(CONFIG_SOFTMMU) && TCG_TARGET_REG_BITS == 64 # if !defined(CONFIG_SOFTMMU)
if (guest_base) { if (guest_base) {
int seg = setup_guest_base_seg(); int seg = setup_guest_base_seg();
if (seg != 0) { if (seg != 0) {
x86_guest_base_seg = seg; x86_guest_base.seg = seg;
} else if (guest_base == (int32_t)guest_base) { } else if (guest_base == (int32_t)guest_base) {
x86_guest_base_offset = guest_base; x86_guest_base.ofs = guest_base;
} else { } else {
/* Choose R12 because, as a base, it requires a SIB byte. */ /* Choose R12 because, as a base, it requires a SIB byte. */
x86_guest_base_index = TCG_REG_R12; x86_guest_base.index = TCG_REG_R12;
tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base_index, guest_base); tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base.index, guest_base);
tcg_regset_set_reg(s->reserved_regs, x86_guest_base_index); tcg_regset_set_reg(s->reserved_regs, x86_guest_base.index);
} }
} }
# endif # endif