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From 67e94ae77f8de4d5d822917f1723cefa7ebfb64d Mon Sep 17 00:00:00 2001
From: Xiantao Zhang <xiantao.zhang@intel.com> Date: Tue, 3 Mar 2009 13:33:13 +0800 Subject: [PATCH] Split ioapic logic from the current apic. Add a new ioapic.c to hold ioapic's logic, and also make it work for ia64. Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com> --- Makefile.target | 2 +- hw/apic.c | 237 +++---------------------------------------------- hw/ioapic.c | 263 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ hw/pc.h | 5 +- 4 files changed, 281 insertions(+), 226 deletions(-) create mode 100644 hw/ioapic.c git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6827 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aliguori
parent
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commit
610626af30
4 changed files with 279 additions and 224 deletions
235
hw/apic.c
235
hw/apic.c
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@ -23,7 +23,6 @@
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#include "host-utils.h"
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//#define DEBUG_APIC
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//#define DEBUG_IOAPIC
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/* APIC Local Vector Table */
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#define APIC_LVT_TIMER 0
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@ -57,8 +56,6 @@
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#define APIC_INPUT_POLARITY (1<<13)
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#define APIC_SEND_PENDING (1<<12)
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#define IOAPIC_NUM_PINS 0x18
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#define ESR_ILLEGAL_ADDRESS (1 << 7)
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#define APIC_SV_ENABLE (1 << 8)
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@ -89,14 +86,6 @@ typedef struct APICState {
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QEMUTimer *timer;
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} APICState;
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struct IOAPICState {
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uint8_t id;
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uint8_t ioregsel;
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uint32_t irr;
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uint64_t ioredtbl[IOAPIC_NUM_PINS];
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};
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static int apic_io_memory;
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static APICState *local_apics[MAX_APICS + 1];
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static int last_apic_id = 0;
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@ -106,6 +95,8 @@ static int apic_irq_delivered;
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static void apic_init_ipi(APICState *s);
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static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
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static void apic_update_irq(APICState *s);
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static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
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uint8_t dest, uint8_t dest_mode);
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/* Find first bit starting from msb */
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static int fls_bit(uint32_t value)
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@ -272,6 +263,17 @@ static void apic_bus_deliver(const uint32_t *deliver_bitmask,
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apic_set_irq(apic_iter, vector_num, trigger_mode) );
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}
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void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
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uint8_t delivery_mode, uint8_t vector_num,
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uint8_t polarity, uint8_t trigger_mode)
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{
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uint32_t deliver_bitmask[MAX_APIC_WORDS];
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apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
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apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
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trigger_mode);
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}
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void cpu_set_apic_base(CPUState *env, uint64_t val)
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{
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APICState *s = env->apic_state;
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@ -923,214 +925,3 @@ int apic_init(CPUState *env)
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return 0;
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}
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static void ioapic_service(IOAPICState *s)
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{
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uint8_t i;
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uint8_t trig_mode;
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uint8_t vector;
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uint8_t delivery_mode;
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uint32_t mask;
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uint64_t entry;
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uint8_t dest;
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uint8_t dest_mode;
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uint8_t polarity;
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uint32_t deliver_bitmask[MAX_APIC_WORDS];
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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mask = 1 << i;
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if (s->irr & mask) {
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entry = s->ioredtbl[i];
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if (!(entry & APIC_LVT_MASKED)) {
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trig_mode = ((entry >> 15) & 1);
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dest = entry >> 56;
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dest_mode = (entry >> 11) & 1;
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delivery_mode = (entry >> 8) & 7;
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polarity = (entry >> 13) & 1;
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if (trig_mode == APIC_TRIGGER_EDGE)
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s->irr &= ~mask;
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if (delivery_mode == APIC_DM_EXTINT)
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vector = pic_read_irq(isa_pic);
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else
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vector = entry & 0xff;
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apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
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apic_bus_deliver(deliver_bitmask, delivery_mode,
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vector, polarity, trig_mode);
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}
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}
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}
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}
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void ioapic_set_irq(void *opaque, int vector, int level)
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{
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IOAPICState *s = opaque;
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/* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
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* to GSI 2. GSI maps to ioapic 1-1. This is not
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* the cleanest way of doing it but it should work. */
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if (vector == 0)
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vector = 2;
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if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
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uint32_t mask = 1 << vector;
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uint64_t entry = s->ioredtbl[vector];
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if ((entry >> 15) & 1) {
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/* level triggered */
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if (level) {
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s->irr |= mask;
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ioapic_service(s);
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} else {
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s->irr &= ~mask;
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}
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} else {
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/* edge triggered */
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if (level) {
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s->irr |= mask;
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ioapic_service(s);
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}
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}
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}
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}
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static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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IOAPICState *s = opaque;
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int index;
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uint32_t val = 0;
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addr &= 0xff;
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if (addr == 0x00) {
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val = s->ioregsel;
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} else if (addr == 0x10) {
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switch (s->ioregsel) {
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case 0x00:
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val = s->id << 24;
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break;
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case 0x01:
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val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
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break;
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case 0x02:
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val = 0;
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break;
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default:
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index = (s->ioregsel - 0x10) >> 1;
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if (index >= 0 && index < IOAPIC_NUM_PINS) {
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if (s->ioregsel & 1)
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val = s->ioredtbl[index] >> 32;
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else
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val = s->ioredtbl[index] & 0xffffffff;
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}
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}
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#ifdef DEBUG_IOAPIC
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printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
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#endif
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}
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return val;
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}
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static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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IOAPICState *s = opaque;
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int index;
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addr &= 0xff;
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if (addr == 0x00) {
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s->ioregsel = val;
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return;
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} else if (addr == 0x10) {
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#ifdef DEBUG_IOAPIC
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printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
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#endif
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switch (s->ioregsel) {
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case 0x00:
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s->id = (val >> 24) & 0xff;
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return;
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case 0x01:
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case 0x02:
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return;
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default:
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index = (s->ioregsel - 0x10) >> 1;
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if (index >= 0 && index < IOAPIC_NUM_PINS) {
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if (s->ioregsel & 1) {
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s->ioredtbl[index] &= 0xffffffff;
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s->ioredtbl[index] |= (uint64_t)val << 32;
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} else {
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s->ioredtbl[index] &= ~0xffffffffULL;
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s->ioredtbl[index] |= val;
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}
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ioapic_service(s);
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}
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}
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}
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}
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static void ioapic_save(QEMUFile *f, void *opaque)
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{
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IOAPICState *s = opaque;
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int i;
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qemu_put_8s(f, &s->id);
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qemu_put_8s(f, &s->ioregsel);
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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qemu_put_be64s(f, &s->ioredtbl[i]);
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}
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}
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static int ioapic_load(QEMUFile *f, void *opaque, int version_id)
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{
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IOAPICState *s = opaque;
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int i;
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if (version_id != 1)
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return -EINVAL;
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qemu_get_8s(f, &s->id);
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qemu_get_8s(f, &s->ioregsel);
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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qemu_get_be64s(f, &s->ioredtbl[i]);
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}
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return 0;
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}
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static void ioapic_reset(void *opaque)
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{
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IOAPICState *s = opaque;
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int i;
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memset(s, 0, sizeof(*s));
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for(i = 0; i < IOAPIC_NUM_PINS; i++)
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s->ioredtbl[i] = 1 << 16; /* mask LVT */
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}
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static CPUReadMemoryFunc *ioapic_mem_read[3] = {
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ioapic_mem_readl,
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ioapic_mem_readl,
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ioapic_mem_readl,
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};
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static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
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ioapic_mem_writel,
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ioapic_mem_writel,
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ioapic_mem_writel,
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};
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IOAPICState *ioapic_init(void)
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{
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IOAPICState *s;
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int io_memory;
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s = qemu_mallocz(sizeof(IOAPICState));
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ioapic_reset(s);
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s->id = last_apic_id++;
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io_memory = cpu_register_io_memory(0, ioapic_mem_read,
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ioapic_mem_write, s);
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cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
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register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
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qemu_register_reset(ioapic_reset, s);
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return s;
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}
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