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tcg: Merge INDEX_op_sub_{i32,i64}

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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-06 22:06:32 -08:00
parent 3f057e2400
commit 60f34f55f1
7 changed files with 12 additions and 18 deletions
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2
docs/devel/tcg-ops.rst
View file

@ -265,7 +265,7 @@ Arithmetic
- | *t0* = *t1* + *t2* - | *t0* = *t1* + *t2*
* - sub_i32/i64 *t0*, *t1*, *t2* * - sub *t0*, *t1*, *t2*
- | *t0* = *t1* - *t2* - | *t0* = *t1* - *t2*

3
include/tcg/tcg-opc.h
View file

@ -47,6 +47,7 @@ DEF(nand, 1, 2, 0, TCG_OPF_INT)
DEF(nor, 1, 2, 0, TCG_OPF_INT) DEF(nor, 1, 2, 0, TCG_OPF_INT)
DEF(or, 1, 2, 0, TCG_OPF_INT) DEF(or, 1, 2, 0, TCG_OPF_INT)
DEF(orc, 1, 2, 0, TCG_OPF_INT) DEF(orc, 1, 2, 0, TCG_OPF_INT)
DEF(sub, 1, 2, 0, TCG_OPF_INT)
DEF(xor, 1, 2, 0, TCG_OPF_INT) DEF(xor, 1, 2, 0, TCG_OPF_INT)
DEF(setcond_i32, 1, 2, 1, 0) DEF(setcond_i32, 1, 2, 1, 0)
@ -62,7 +63,6 @@ DEF(st8_i32, 0, 2, 1, 0)
DEF(st16_i32, 0, 2, 1, 0) DEF(st16_i32, 0, 2, 1, 0)
DEF(st_i32, 0, 2, 1, 0) DEF(st_i32, 0, 2, 1, 0)
/* arith */ /* arith */
DEF(sub_i32, 1, 2, 0, 0)
DEF(mul_i32, 1, 2, 0, 0) DEF(mul_i32, 1, 2, 0, 0)
DEF(div_i32, 1, 2, 0, 0) DEF(div_i32, 1, 2, 0, 0)
DEF(divu_i32, 1, 2, 0, 0) DEF(divu_i32, 1, 2, 0, 0)
@ -116,7 +116,6 @@ DEF(st16_i64, 0, 2, 1, 0)
DEF(st32_i64, 0, 2, 1, 0) DEF(st32_i64, 0, 2, 1, 0)
DEF(st_i64, 0, 2, 1, 0) DEF(st_i64, 0, 2, 1, 0)
/* arith */ /* arith */
DEF(sub_i64, 1, 2, 0, 0)
DEF(mul_i64, 1, 2, 0, 0) DEF(mul_i64, 1, 2, 0, 0)
DEF(div_i64, 1, 2, 0, 0) DEF(div_i64, 1, 2, 0, 0)
DEF(divu_i64, 1, 2, 0, 0) DEF(divu_i64, 1, 2, 0, 0)

4
tcg/optimize.c
View file

@ -427,7 +427,7 @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
case INDEX_op_add: case INDEX_op_add:
return x + y; return x + y;
CASE_OP_32_64(sub): case INDEX_op_sub:
return x - y; return x - y;
CASE_OP_32_64(mul): CASE_OP_32_64(mul):
@ -3066,7 +3066,7 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(sextract): CASE_OP_32_64(sextract):
done = fold_sextract(&ctx, op); done = fold_sextract(&ctx, op);
break; break;
CASE_OP_32_64(sub): case INDEX_op_sub:
done = fold_sub(&ctx, op); done = fold_sub(&ctx, op);
break; break;
case INDEX_op_sub_vec: case INDEX_op_sub_vec:

4
tcg/tcg-op.c
View file

@ -377,7 +377,7 @@ void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{ {
tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); tcg_gen_op3_i32(INDEX_op_sub, ret, arg1, arg2);
} }
void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
@ -1565,7 +1565,7 @@ void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
{ {
if (TCG_TARGET_REG_BITS == 64) { if (TCG_TARGET_REG_BITS == 64) {
tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); tcg_gen_op3_i64(INDEX_op_sub, ret, arg1, arg2);
} else { } else {
tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2)); TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));

10
tcg/tcg.c
View file

@ -1020,8 +1020,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_nor, TCGOutOpBinary, outop_nor), OUTOP(INDEX_op_nor, TCGOutOpBinary, outop_nor),
OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or), OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or),
OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc), OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc),
OUTOP(INDEX_op_sub_i32, TCGOutOpSubtract, outop_sub), OUTOP(INDEX_op_sub, TCGOutOpSubtract, outop_sub),
OUTOP(INDEX_op_sub_i64, TCGOutOpSubtract, outop_sub),
OUTOP(INDEX_op_xor, TCGOutOpBinary, outop_xor), OUTOP(INDEX_op_xor, TCGOutOpBinary, outop_xor),
}; };
@ -4010,10 +4009,8 @@ liveness_pass_1(TCGContext *s)
opc_new = INDEX_op_add; opc_new = INDEX_op_add;
goto do_addsub2; goto do_addsub2;
case INDEX_op_sub2_i32: case INDEX_op_sub2_i32:
opc_new = INDEX_op_sub_i32;
goto do_addsub2;
case INDEX_op_sub2_i64: case INDEX_op_sub2_i64:
opc_new = INDEX_op_sub_i64; opc_new = INDEX_op_sub;
do_addsub2: do_addsub2:
nb_iargs = 4; nb_iargs = 4;
nb_oargs = 2; nb_oargs = 2;
@ -5457,8 +5454,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
} }
break; break;
case INDEX_op_sub_i32: case INDEX_op_sub:
case INDEX_op_sub_i64:
{ {
const TCGOutOpSubtract *out = &outop_sub; const TCGOutOpSubtract *out = &outop_sub;

5
tcg/tci.c
View file

@ -527,7 +527,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrr(insn, &r0, &r1, &r2); tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] + regs[r2]; regs[r0] = regs[r1] + regs[r2];
break; break;
CASE_32_64(sub) case INDEX_op_sub:
tci_args_rrr(insn, &r0, &r1, &r2); tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] - regs[r2]; regs[r0] = regs[r1] - regs[r2];
break; break;
@ -1080,9 +1080,8 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_nor: case INDEX_op_nor:
case INDEX_op_or: case INDEX_op_or:
case INDEX_op_orc: case INDEX_op_orc:
case INDEX_op_sub:
case INDEX_op_xor: case INDEX_op_xor:
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
case INDEX_op_mul_i32: case INDEX_op_mul_i32:
case INDEX_op_mul_i64: case INDEX_op_mul_i64:
case INDEX_op_div_i32: case INDEX_op_div_i32:

2
tcg/tci/tcg-target.c.inc
View file

@ -712,7 +712,7 @@ static const TCGOutOpBinary outop_orc = {
static void tgen_sub(TCGContext *s, TCGType type, static void tgen_sub(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2) TCGReg a0, TCGReg a1, TCGReg a2)
{ {
tcg_out_op_rrr(s, glue(INDEX_op_sub_i,TCG_TARGET_REG_BITS), a0, a1, a2); tcg_out_op_rrr(s, INDEX_op_sub, a0, a1, a2);
} }
static const TCGOutOpSubtract outop_sub = { static const TCGOutOpSubtract outop_sub = {