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RISC-V PR for 10.0
* Correct the validness check of iova * Fix APLIC in_clrip and clripnum write emulation * Support riscv-iommu-sys device * Add Tenstorrent Ascalon CPU * Add AIA userspace irqchip_split support * Add Microblaze V generic board * Upgrade ACPI SPCR table to support SPCR table revision 4 format * Remove tswap64() calls from HTIF * Support 64-bit address of initrd * Introduce svukte ISA extension * Support ssstateen extension * Support for RV64 Xiangshan Nanhu CPU -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmdkzjgACgkQr3yVEwxT gBOcyA//e0XhAQciQglCZZCfINdOyI8qSh+P2K0qtrXZ4VERHEMp7UoD5CQr2cZv h8ij1EkatXCwukVELx0rNckxG33bEFgG1oESnQSrwGE0Iu4csNW24nK5WlUS0/r+ A5oD2wtzEF+cbhTKrVSDBN/PvlnWTKGEoJRkuXWfz5d4uR9eyQhfED0S2j36lNEC X1x/OZoKM89XuXtOFe9g55Z5UNzAatcdTISozL0FydiPh7QeVjTLHh28/tt559MX 7v5aJFlQuZ78z1mIHkZmPSorSrJ0zqhkP6NWe1ae06oMgzwRQQhYLppDILV4ZgUF 3mSDRoXmBycQXiYNPcHep3LdXfvxr+PpWHSevx8gH1jwm93On7Y/H7Uol6TDXzfC mrFjalfV5tzrD90ZvB+s5bCMF1q5Z8Dlj0pYF9aN9P1ILoWy3dndFAPJB6uKKDP7 Qd4qOQ3dVyHAX9jLmVkB6QvAV/vTDrYTsAxaF/EaoLOy0IoKhjTvgda3XzE1MFKA gVafLluADIfSEdqa2QR2ExL8d1SZVoiObCp5TMLRer0HIpg/vQZwjfdbo4BgQKL3 7Q6wBxcZUNqrFgspXjm5WFIrdk2rfS/79OmvpNM6SZaK6BnklntdJHJHtAWujGsm EM310AUFpHMp2h6Nqnemb3qr5l4d20KSt8DhoPAUq1IE59Kb8XY= =0iQW -----END PGP SIGNATURE----- Merge tag 'pull-riscv-to-apply-20241220' of https://github.com/alistair23/qemu into staging RISC-V PR for 10.0 * Correct the validness check of iova * Fix APLIC in_clrip and clripnum write emulation * Support riscv-iommu-sys device * Add Tenstorrent Ascalon CPU * Add AIA userspace irqchip_split support * Add Microblaze V generic board * Upgrade ACPI SPCR table to support SPCR table revision 4 format * Remove tswap64() calls from HTIF * Support 64-bit address of initrd * Introduce svukte ISA extension * Support ssstateen extension * Support for RV64 Xiangshan Nanhu CPU # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmdkzjgACgkQr3yVEwxT # gBOcyA//e0XhAQciQglCZZCfINdOyI8qSh+P2K0qtrXZ4VERHEMp7UoD5CQr2cZv # h8ij1EkatXCwukVELx0rNckxG33bEFgG1oESnQSrwGE0Iu4csNW24nK5WlUS0/r+ # A5oD2wtzEF+cbhTKrVSDBN/PvlnWTKGEoJRkuXWfz5d4uR9eyQhfED0S2j36lNEC # X1x/OZoKM89XuXtOFe9g55Z5UNzAatcdTISozL0FydiPh7QeVjTLHh28/tt559MX # 7v5aJFlQuZ78z1mIHkZmPSorSrJ0zqhkP6NWe1ae06oMgzwRQQhYLppDILV4ZgUF # 3mSDRoXmBycQXiYNPcHep3LdXfvxr+PpWHSevx8gH1jwm93On7Y/H7Uol6TDXzfC # mrFjalfV5tzrD90ZvB+s5bCMF1q5Z8Dlj0pYF9aN9P1ILoWy3dndFAPJB6uKKDP7 # Qd4qOQ3dVyHAX9jLmVkB6QvAV/vTDrYTsAxaF/EaoLOy0IoKhjTvgda3XzE1MFKA # gVafLluADIfSEdqa2QR2ExL8d1SZVoiObCp5TMLRer0HIpg/vQZwjfdbo4BgQKL3 # 7Q6wBxcZUNqrFgspXjm5WFIrdk2rfS/79OmvpNM6SZaK6BnklntdJHJHtAWujGsm # EM310AUFpHMp2h6Nqnemb3qr5l4d20KSt8DhoPAUq1IE59Kb8XY= # =0iQW # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Dec 2024 20:54:00 EST # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20241220' of https://github.com/alistair23/qemu: (39 commits) target/riscv: add support for RV64 Xiangshan Nanhu CPU target/riscv: add ssstateen target/riscv/tcg: hide warn for named feats when disabling via priv_ver target/riscv: Include missing headers in 'internals.h' target/riscv: Include missing headers in 'vector_internals.h' target/riscv: Check svukte is not enabled in RV32 target/riscv: Expose svukte ISA extension target/riscv: Check memory access to meet svukte rule target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled target/riscv: Add svukte extension capability variable hw/riscv: Add the checking if DTB overlaps to kernel or initrd hw/riscv: Add a new struct RISCVBootInfo hw/riscv: Support to load DTB after 3GB memory on 64-bit system. hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses hw/char/riscv_htif: Explicit little-endian implementation MAINTAINERS: Cover RISC-V HTIF interface tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format qtest: allow SPCR acpi table changes ... Conflicts: target/riscv/cpu.c Merge conflict with DEFINE_PROP_END_OF_LIST() removal. No Property array terminator is needed anymore. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
commit
60a07d4a6e
46 changed files with 1381 additions and 178 deletions
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@ -112,7 +112,6 @@ typedef struct AcpiSpcrData {
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uint8_t flow_control;
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uint8_t terminal_type;
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uint8_t language;
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uint8_t reserved1;
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uint16_t pci_device_id; /* Must be 0xffff if not PCI device */
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uint16_t pci_vendor_id; /* Must be 0xffff if not PCI device */
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uint8_t pci_bus;
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@ -120,7 +119,11 @@ typedef struct AcpiSpcrData {
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uint8_t pci_function;
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uint32_t pci_flags;
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uint8_t pci_segment;
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uint32_t reserved2;
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uint32_t uart_clk_freq;
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uint32_t precise_baudrate;
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uint32_t namespace_string_length;
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uint32_t namespace_string_offset;
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char namespace_string[];
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} AcpiSpcrData;
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#define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0)
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@ -507,5 +507,5 @@ void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
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void build_spcr(GArray *table_data, BIOSLinker *linker,
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const AcpiSpcrData *f, const uint8_t rev,
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const char *oem_id, const char *oem_table_id);
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const char *oem_id, const char *oem_table_id, const char *name);
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#endif
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@ -68,9 +68,17 @@ struct RISCVAPLICState {
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uint32_t num_irqs;
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bool msimode;
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bool mmode;
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/* To support KVM aia=aplic-imsic with irqchip split mode */
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bool kvm_splitmode;
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uint32_t kvm_msicfgaddr;
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uint32_t kvm_msicfgaddrH;
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};
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void riscv_aplic_add_child(DeviceState *parent, DeviceState *child);
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bool riscv_is_kvm_aia_aplic_imsic(bool msimode);
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bool riscv_use_emulated_aplic(bool msimode);
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void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *aplic, hwaddr addr);
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DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
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uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
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@ -27,11 +27,23 @@
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#define RISCV32_BIOS_BIN "opensbi-riscv32-generic-fw_dynamic.bin"
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#define RISCV64_BIOS_BIN "opensbi-riscv64-generic-fw_dynamic.bin"
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typedef struct RISCVBootInfo {
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ssize_t kernel_size;
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hwaddr image_low_addr;
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hwaddr image_high_addr;
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hwaddr initrd_start;
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ssize_t initrd_size;
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bool is_32bit;
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} RISCVBootInfo;
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bool riscv_is_32bit(RISCVHartArrayState *harts);
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char *riscv_plic_hart_config_string(int hart_count);
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target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
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void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts);
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target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info,
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target_ulong firmware_end_addr);
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target_ulong riscv_find_and_load_firmware(MachineState *machine,
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const char *default_machine_firmware,
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@ -43,13 +55,13 @@ char *riscv_find_firmware(const char *firmware_filename,
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target_ulong riscv_load_firmware(const char *firmware_filename,
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hwaddr *firmware_load_addr,
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symbol_fn_t sym_cb);
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target_ulong riscv_load_kernel(MachineState *machine,
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RISCVHartArrayState *harts,
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target_ulong firmware_end_addr,
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bool load_initrd,
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symbol_fn_t sym_cb);
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uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size,
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MachineState *ms);
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void riscv_load_kernel(MachineState *machine,
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RISCVBootInfo *info,
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target_ulong kernel_start_addr,
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bool load_initrd,
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symbol_fn_t sym_cb);
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uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
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MachineState *ms, RISCVBootInfo *info);
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void riscv_load_fdt(hwaddr fdt_addr, void *fdt);
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void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
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hwaddr saddr,
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@ -30,7 +30,15 @@ typedef struct RISCVIOMMUState RISCVIOMMUState;
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typedef struct RISCVIOMMUSpace RISCVIOMMUSpace;
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#define TYPE_RISCV_IOMMU_PCI "riscv-iommu-pci"
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OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStatePci, RISCV_IOMMU_PCI)
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OBJECT_DECLARE_TYPE(RISCVIOMMUStatePci, RISCVIOMMUPciClass, RISCV_IOMMU_PCI)
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typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci;
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typedef struct RISCVIOMMUPciClass RISCVIOMMUPciClass;
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#define TYPE_RISCV_IOMMU_SYS "riscv-iommu-device"
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OBJECT_DECLARE_TYPE(RISCVIOMMUStateSys, RISCVIOMMUSysClass, RISCV_IOMMU_SYS)
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typedef struct RISCVIOMMUStateSys RISCVIOMMUStateSys;
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typedef struct RISCVIOMMUSysClass RISCVIOMMUSysClass;
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#define FDT_IRQ_TYPE_EDGE_LOW 1
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#endif
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@ -62,6 +62,7 @@ struct RISCVVirtState {
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OnOffAuto acpi;
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const MemMapEntry *memmap;
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struct GPEXHost *gpex_host;
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OnOffAuto iommu_sys;
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};
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enum {
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@ -84,7 +85,8 @@ enum {
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VIRT_PCIE_MMIO,
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VIRT_PCIE_PIO,
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VIRT_PLATFORM_BUS,
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VIRT_PCIE_ECAM
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VIRT_PCIE_ECAM,
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VIRT_IOMMU_SYS,
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};
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enum {
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@ -93,6 +95,7 @@ enum {
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VIRTIO_IRQ = 1, /* 1 to 8 */
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VIRTIO_COUNT = 8,
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PCIE_IRQ = 0x20, /* 32 to 35 */
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IOMMU_SYS_IRQ = 0x24, /* 36-39 */
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VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 95 */
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};
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@ -129,6 +132,7 @@ enum {
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1 + FDT_APLIC_INT_CELLS)
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bool virt_is_acpi_enabled(RISCVVirtState *s);
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bool virt_is_iommu_sys_enabled(RISCVVirtState *s);
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void virt_acpi_setup(RISCVVirtState *vms);
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uint32_t imsic_num_bits(uint32_t count);
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