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RISC-V PR for 10.0
* Correct the validness check of iova * Fix APLIC in_clrip and clripnum write emulation * Support riscv-iommu-sys device * Add Tenstorrent Ascalon CPU * Add AIA userspace irqchip_split support * Add Microblaze V generic board * Upgrade ACPI SPCR table to support SPCR table revision 4 format * Remove tswap64() calls from HTIF * Support 64-bit address of initrd * Introduce svukte ISA extension * Support ssstateen extension * Support for RV64 Xiangshan Nanhu CPU -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmdkzjgACgkQr3yVEwxT gBOcyA//e0XhAQciQglCZZCfINdOyI8qSh+P2K0qtrXZ4VERHEMp7UoD5CQr2cZv h8ij1EkatXCwukVELx0rNckxG33bEFgG1oESnQSrwGE0Iu4csNW24nK5WlUS0/r+ A5oD2wtzEF+cbhTKrVSDBN/PvlnWTKGEoJRkuXWfz5d4uR9eyQhfED0S2j36lNEC X1x/OZoKM89XuXtOFe9g55Z5UNzAatcdTISozL0FydiPh7QeVjTLHh28/tt559MX 7v5aJFlQuZ78z1mIHkZmPSorSrJ0zqhkP6NWe1ae06oMgzwRQQhYLppDILV4ZgUF 3mSDRoXmBycQXiYNPcHep3LdXfvxr+PpWHSevx8gH1jwm93On7Y/H7Uol6TDXzfC mrFjalfV5tzrD90ZvB+s5bCMF1q5Z8Dlj0pYF9aN9P1ILoWy3dndFAPJB6uKKDP7 Qd4qOQ3dVyHAX9jLmVkB6QvAV/vTDrYTsAxaF/EaoLOy0IoKhjTvgda3XzE1MFKA gVafLluADIfSEdqa2QR2ExL8d1SZVoiObCp5TMLRer0HIpg/vQZwjfdbo4BgQKL3 7Q6wBxcZUNqrFgspXjm5WFIrdk2rfS/79OmvpNM6SZaK6BnklntdJHJHtAWujGsm EM310AUFpHMp2h6Nqnemb3qr5l4d20KSt8DhoPAUq1IE59Kb8XY= =0iQW -----END PGP SIGNATURE----- Merge tag 'pull-riscv-to-apply-20241220' of https://github.com/alistair23/qemu into staging RISC-V PR for 10.0 * Correct the validness check of iova * Fix APLIC in_clrip and clripnum write emulation * Support riscv-iommu-sys device * Add Tenstorrent Ascalon CPU * Add AIA userspace irqchip_split support * Add Microblaze V generic board * Upgrade ACPI SPCR table to support SPCR table revision 4 format * Remove tswap64() calls from HTIF * Support 64-bit address of initrd * Introduce svukte ISA extension * Support ssstateen extension * Support for RV64 Xiangshan Nanhu CPU # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmdkzjgACgkQr3yVEwxT # gBOcyA//e0XhAQciQglCZZCfINdOyI8qSh+P2K0qtrXZ4VERHEMp7UoD5CQr2cZv # h8ij1EkatXCwukVELx0rNckxG33bEFgG1oESnQSrwGE0Iu4csNW24nK5WlUS0/r+ # A5oD2wtzEF+cbhTKrVSDBN/PvlnWTKGEoJRkuXWfz5d4uR9eyQhfED0S2j36lNEC # X1x/OZoKM89XuXtOFe9g55Z5UNzAatcdTISozL0FydiPh7QeVjTLHh28/tt559MX # 7v5aJFlQuZ78z1mIHkZmPSorSrJ0zqhkP6NWe1ae06oMgzwRQQhYLppDILV4ZgUF # 3mSDRoXmBycQXiYNPcHep3LdXfvxr+PpWHSevx8gH1jwm93On7Y/H7Uol6TDXzfC # mrFjalfV5tzrD90ZvB+s5bCMF1q5Z8Dlj0pYF9aN9P1ILoWy3dndFAPJB6uKKDP7 # Qd4qOQ3dVyHAX9jLmVkB6QvAV/vTDrYTsAxaF/EaoLOy0IoKhjTvgda3XzE1MFKA # gVafLluADIfSEdqa2QR2ExL8d1SZVoiObCp5TMLRer0HIpg/vQZwjfdbo4BgQKL3 # 7Q6wBxcZUNqrFgspXjm5WFIrdk2rfS/79OmvpNM6SZaK6BnklntdJHJHtAWujGsm # EM310AUFpHMp2h6Nqnemb3qr5l4d20KSt8DhoPAUq1IE59Kb8XY= # =0iQW # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Dec 2024 20:54:00 EST # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20241220' of https://github.com/alistair23/qemu: (39 commits) target/riscv: add support for RV64 Xiangshan Nanhu CPU target/riscv: add ssstateen target/riscv/tcg: hide warn for named feats when disabling via priv_ver target/riscv: Include missing headers in 'internals.h' target/riscv: Include missing headers in 'vector_internals.h' target/riscv: Check svukte is not enabled in RV32 target/riscv: Expose svukte ISA extension target/riscv: Check memory access to meet svukte rule target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled target/riscv: Add svukte extension capability variable hw/riscv: Add the checking if DTB overlaps to kernel or initrd hw/riscv: Add a new struct RISCVBootInfo hw/riscv: Support to load DTB after 3GB memory on 64-bit system. hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses hw/char/riscv_htif: Explicit little-endian implementation MAINTAINERS: Cover RISC-V HTIF interface tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format qtest: allow SPCR acpi table changes ... Conflicts: target/riscv/cpu.c Merge conflict with DEFINE_PROP_END_OF_LIST() removal. No Property array terminator is needed anymore. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
commit
60a07d4a6e
46 changed files with 1381 additions and 178 deletions
255
hw/riscv/riscv-iommu-sys.c
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255
hw/riscv/riscv-iommu-sys.c
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/*
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* QEMU emulation of an RISC-V IOMMU Platform Device
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*
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* Copyright (C) 2022-2023 Rivos Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "qemu/host-utils.h"
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#include "qemu/module.h"
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#include "qom/object.h"
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#include "exec/exec-all.h"
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#include "trace.h"
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#include "riscv-iommu.h"
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#define RISCV_IOMMU_SYSDEV_ICVEC_VECTORS 0x3333
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#define RISCV_IOMMU_PCI_MSIX_VECTORS 5
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/* RISC-V IOMMU System Platform Device Emulation */
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struct RISCVIOMMUStateSys {
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SysBusDevice parent;
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uint64_t addr;
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uint32_t base_irq;
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DeviceState *irqchip;
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RISCVIOMMUState iommu;
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/* Wired int support */
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qemu_irq irqs[RISCV_IOMMU_INTR_COUNT];
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/* Memory Regions for MSIX table and pending bit entries. */
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MemoryRegion msix_table_mmio;
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MemoryRegion msix_pba_mmio;
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uint8_t *msix_table;
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uint8_t *msix_pba;
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};
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struct RISCVIOMMUSysClass {
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/*< public >*/
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DeviceRealize parent_realize;
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ResettablePhases parent_phases;
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};
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static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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RISCVIOMMUStateSys *s = opaque;
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g_assert(addr + size <= RISCV_IOMMU_PCI_MSIX_VECTORS * PCI_MSIX_ENTRY_SIZE);
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return pci_get_long(s->msix_table + addr);
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}
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static void msix_table_mmio_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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RISCVIOMMUStateSys *s = opaque;
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g_assert(addr + size <= RISCV_IOMMU_PCI_MSIX_VECTORS * PCI_MSIX_ENTRY_SIZE);
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pci_set_long(s->msix_table + addr, val);
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}
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static const MemoryRegionOps msix_table_mmio_ops = {
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.read = msix_table_mmio_read,
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.write = msix_table_mmio_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 8,
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},
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.impl = {
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.max_access_size = 4,
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},
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};
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static uint64_t msix_pba_mmio_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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RISCVIOMMUStateSys *s = opaque;
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return pci_get_long(s->msix_pba + addr);
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}
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static void msix_pba_mmio_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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}
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static const MemoryRegionOps msix_pba_mmio_ops = {
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.read = msix_pba_mmio_read,
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.write = msix_pba_mmio_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 8,
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},
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.impl = {
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.max_access_size = 4,
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},
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};
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static void riscv_iommu_sysdev_init_msi(RISCVIOMMUStateSys *s,
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uint32_t n_vectors)
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{
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RISCVIOMMUState *iommu = &s->iommu;
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uint32_t table_size = table_size = n_vectors * PCI_MSIX_ENTRY_SIZE;
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uint32_t table_offset = RISCV_IOMMU_REG_MSI_CONFIG;
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uint32_t pba_size = QEMU_ALIGN_UP(n_vectors, 64) / 8;
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uint32_t pba_offset = RISCV_IOMMU_REG_MSI_CONFIG + 256;
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s->msix_table = g_malloc0(table_size);
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s->msix_pba = g_malloc0(pba_size);
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memory_region_init_io(&s->msix_table_mmio, OBJECT(s), &msix_table_mmio_ops,
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s, "msix-table", table_size);
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memory_region_add_subregion(&iommu->regs_mr, table_offset,
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&s->msix_table_mmio);
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memory_region_init_io(&s->msix_pba_mmio, OBJECT(s), &msix_pba_mmio_ops, s,
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"msix-pba", pba_size);
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memory_region_add_subregion(&iommu->regs_mr, pba_offset,
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&s->msix_pba_mmio);
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}
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static void riscv_iommu_sysdev_send_MSI(RISCVIOMMUStateSys *s,
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uint32_t vector)
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{
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uint8_t *table_entry = s->msix_table + vector * PCI_MSIX_ENTRY_SIZE;
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uint64_t msi_addr = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
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uint32_t msi_data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
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MemTxResult result;
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address_space_stl_le(&address_space_memory, msi_addr,
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msi_data, MEMTXATTRS_UNSPECIFIED, &result);
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trace_riscv_iommu_sys_msi_sent(vector, msi_addr, msi_data, result);
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}
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static void riscv_iommu_sysdev_notify(RISCVIOMMUState *iommu,
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unsigned vector)
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{
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RISCVIOMMUStateSys *s = container_of(iommu, RISCVIOMMUStateSys, iommu);
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uint32_t fctl = riscv_iommu_reg_get32(iommu, RISCV_IOMMU_REG_FCTL);
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if (fctl & RISCV_IOMMU_FCTL_WSI) {
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qemu_irq_pulse(s->irqs[vector]);
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trace_riscv_iommu_sys_irq_sent(vector);
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return;
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}
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riscv_iommu_sysdev_send_MSI(s, vector);
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}
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static void riscv_iommu_sys_realize(DeviceState *dev, Error **errp)
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{
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RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(dev);
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SysBusDevice *sysdev = SYS_BUS_DEVICE(s);
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PCIBus *pci_bus;
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qemu_irq irq;
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qdev_realize(DEVICE(&s->iommu), NULL, errp);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iommu.regs_mr);
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if (s->addr) {
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sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, s->addr);
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}
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pci_bus = (PCIBus *) object_resolve_path_type("", TYPE_PCI_BUS, NULL);
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if (pci_bus) {
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riscv_iommu_pci_setup_iommu(&s->iommu, pci_bus, errp);
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}
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s->iommu.notify = riscv_iommu_sysdev_notify;
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/* 4 IRQs are defined starting from s->base_irq */
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for (int i = 0; i < RISCV_IOMMU_INTR_COUNT; i++) {
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sysbus_init_irq(sysdev, &s->irqs[i]);
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irq = qdev_get_gpio_in(s->irqchip, s->base_irq + i);
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sysbus_connect_irq(sysdev, i, irq);
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}
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riscv_iommu_sysdev_init_msi(s, RISCV_IOMMU_PCI_MSIX_VECTORS);
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}
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static void riscv_iommu_sys_init(Object *obj)
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{
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RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(obj);
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RISCVIOMMUState *iommu = &s->iommu;
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object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU);
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qdev_alias_all_properties(DEVICE(iommu), obj);
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iommu->icvec_avail_vectors = RISCV_IOMMU_SYSDEV_ICVEC_VECTORS;
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riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_BOTH);
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}
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static const Property riscv_iommu_sys_properties[] = {
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DEFINE_PROP_UINT64("addr", RISCVIOMMUStateSys, addr, 0),
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DEFINE_PROP_UINT32("base-irq", RISCVIOMMUStateSys, base_irq, 0),
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DEFINE_PROP_LINK("irqchip", RISCVIOMMUStateSys, irqchip,
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TYPE_DEVICE, DeviceState *),
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};
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static void riscv_iommu_sys_reset_hold(Object *obj, ResetType type)
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{
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RISCVIOMMUStateSys *sys = RISCV_IOMMU_SYS(obj);
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RISCVIOMMUState *iommu = &sys->iommu;
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riscv_iommu_reset(iommu);
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trace_riscv_iommu_sys_reset_hold(type);
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}
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static void riscv_iommu_sys_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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rc->phases.hold = riscv_iommu_sys_reset_hold;
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dc->realize = riscv_iommu_sys_realize;
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set_bit(DEVICE_CATEGORY_MISC, dc->categories);
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device_class_set_props(dc, riscv_iommu_sys_properties);
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}
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static const TypeInfo riscv_iommu_sys = {
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.name = TYPE_RISCV_IOMMU_SYS,
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.parent = TYPE_SYS_BUS_DEVICE,
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.class_init = riscv_iommu_sys_class_init,
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.instance_init = riscv_iommu_sys_init,
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.instance_size = sizeof(RISCVIOMMUStateSys),
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};
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static void riscv_iommu_register_sys(void)
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{
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type_register_static(&riscv_iommu_sys);
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}
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type_init(riscv_iommu_register_sys)
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