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RISC-V PR for 10.0

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* Correct the validness check of iova
 * Fix APLIC in_clrip and clripnum write emulation
 * Support riscv-iommu-sys device
 * Add Tenstorrent Ascalon CPU
 * Add AIA userspace irqchip_split support
 * Add Microblaze V generic board
 * Upgrade ACPI SPCR table to support SPCR table revision 4 format
 * Remove tswap64() calls from HTIF
 * Support 64-bit address of initrd
 * Introduce svukte ISA extension
 * Support ssstateen extension
 * Support for RV64 Xiangshan Nanhu CPU
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Merge tag 'pull-riscv-to-apply-20241220' of https://github.com/alistair23/qemu into staging

RISC-V PR for 10.0

* Correct the validness check of iova
* Fix APLIC in_clrip and clripnum write emulation
* Support riscv-iommu-sys device
* Add Tenstorrent Ascalon CPU
* Add AIA userspace irqchip_split support
* Add Microblaze V generic board
* Upgrade ACPI SPCR table to support SPCR table revision 4 format
* Remove tswap64() calls from HTIF
* Support 64-bit address of initrd
* Introduce svukte ISA extension
* Support ssstateen extension
* Support for RV64 Xiangshan Nanhu CPU

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 # gpg:                using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
 # gpg: WARNING: This key is not certified with a trusted signature!
 # gpg:          There is no indication that the signature belongs to the owner.
 # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65  9296 AF7C 9513 0C53 8013

* tag 'pull-riscv-to-apply-20241220' of https://github.com/alistair23/qemu: (39 commits)
  target/riscv: add support for RV64 Xiangshan Nanhu CPU
  target/riscv: add ssstateen
  target/riscv/tcg: hide warn for named feats when disabling via priv_ver
  target/riscv: Include missing headers in 'internals.h'
  target/riscv: Include missing headers in 'vector_internals.h'
  target/riscv: Check svukte is not enabled in RV32
  target/riscv: Expose svukte ISA extension
  target/riscv: Check memory access to meet svukte rule
  target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled
  target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled
  target/riscv: Add svukte extension capability variable
  hw/riscv: Add the checking if DTB overlaps to kernel or initrd
  hw/riscv: Add a new struct RISCVBootInfo
  hw/riscv: Support to load DTB after 3GB memory on 64-bit system.
  hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses
  hw/char/riscv_htif: Explicit little-endian implementation
  MAINTAINERS: Cover RISC-V HTIF interface
  tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V
  hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format
  qtest: allow SPCR acpi table changes
  ...

Conflicts:
  target/riscv/cpu.c

  Merge conflict with DEFINE_PROP_END_OF_LIST() removal. No Property
  array terminator is needed anymore.

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2024-12-21 08:13:16 -05:00
commit 60a07d4a6e
46 changed files with 1381 additions and 178 deletions
Download patch file Download diff file Expand all files Collapse all files

1
docs/specs/index.rst
View file

@ -37,3 +37,4 @@ guest hardware that is specific to QEMU.
rapl-msr
rocker
riscv-iommu
riscv-aia

83
docs/specs/riscv-aia.rst Normal file
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@ -0,0 +1,83 @@
.. _riscv-aia:
RISC-V AIA support for RISC-V machines
======================================
AIA (Advanced Interrupt Architecture) support is implemented in the ``virt``
RISC-V machine for TCG and KVM accelerators.
The support consists of two main modes:
- "aia=aplic": adds one or more APLIC (Advanced Platform Level Interrupt Controller)
devices
- "aia=aplic-imsic": adds one or more APLIC device and an IMSIC (Incoming MSI
Controller) device for each CPU
From an user standpoint, these modes will behave the same regardless of the accelerator
used. From a developer standpoint the accelerator settings will change what it being
emulated in userspace versus what is being emulated by an in-kernel irqchip.
When running TCG, all controllers are emulated in userspace, including machine mode
(m-mode) APLIC and IMSIC (when applicable).
When running KVM:
- no m-mode is provided, so there is no m-mode APLIC or IMSIC emulation regardless of
the AIA mode chosen
- with "aia=aplic", s-mode APLIC will be emulated by userspace
- with "aia=aplic-imsic" there are two possibilities. If no additional KVM option
is provided there will be no APLIC or IMSIC emulation in userspace, and the virtual
machine will use the provided in-kernel APLIC and IMSIC controllers. If the user
chooses to use the irqchip in split mode via "-accel kvm,kernel-irqchip=split",
s-mode APLIC will be emulated while using the s-mode IMSIC from the irqchip
The following table summarizes how the AIA and accelerator options defines what
we will emulate in userspace:
.. list-table:: How AIA and accel options changes controller emulation
:widths: 25 25 25 25 25 25 25
:header-rows: 1
* - Accel
- Accel props
- AIA type
- APLIC m-mode
- IMSIC m-mode
- APLIC s-mode
- IMSIC s-mode
* - tcg
- ---
- aplic
- emul
- n/a
- emul
- n/a
* - tcg
- ---
- aplic-imsic
- emul
- emul
- emul
- emul
* - kvm
- ---
- aplic
- n/a
- n/a
- emul
- n/a
* - kvm
- none
- aplic-imsic
- n/a
- n/a
- in-kernel
- in-kernel
* - kvm
- irqchip=split
- aplic-imsic
- n/a
- n/a
- emul
- in-kernel

30
docs/specs/riscv-iommu.rst
View file

@ -6,9 +6,9 @@ RISC-V IOMMU support for RISC-V machines
QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec
version 1.0 `iommu1.0`_.
The emulation includes a PCI reference device, riscv-iommu-pci, that QEMU
RISC-V boards can use. The 'virt' RISC-V machine is compatible with this
device.
The emulation includes a PCI reference device (riscv-iommu-pci) and a platform
bus device (riscv-iommu-sys) that QEMU RISC-V boards can use. The 'virt'
RISC-V machine is compatible with both devices.
riscv-iommu-pci reference device
--------------------------------
@ -83,6 +83,30 @@ Several options are available to control the capabilities of the device, namely:
- "s-stage": enable s-stage support
- "g-stage": enable g-stage support
riscv-iommu-sys device
----------------------
This device implements the RISC-V IOMMU emulation as a platform bus device that
RISC-V boards can use.
For the 'virt' board the device is disabled by default. To enable it use the
'iommu-sys' machine option:
.. code-block:: bash
$ qemu-system-riscv64 -M virt,iommu-sys=on (...)
There is no options to configure the capabilities of this device in the 'virt'
board using the QEMU command line. The device is configured with the following
riscv-iommu options:
- "ioatc-limit": default value (2Mb)
- "intremap": enabled
- "ats": enabled
- "off": on (DMA disabled)
- "s-stage": enabled
- "g-stage": enabled
.. _iommu1.0: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf
.. _linux-v8: https://lore.kernel.org/linux-riscv/cover.1718388908.git.tjeznach@rivosinc.com/

42
docs/system/riscv/microblaze-v-generic.rst Normal file
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@ -0,0 +1,42 @@
Microblaze-V generic board (``amd-microblaze-v-generic``)
=========================================================
The AMD MicroBlaze™ V processor is a soft-core RISC-V processor IP for AMD
adaptive SoCs and FPGAs. The MicroBlaze™ V processor is based on the 32-bit (or
64-bit) RISC-V instruction set architecture (ISA) and contains interfaces
compatible with the classic MicroBlaze™ V processor (i.e it is a drop in
replacement for the classic MicroBlaze™ processor in existing RTL designs).
More information can be found in below document.
https://docs.amd.com/r/en-US/ug1629-microblaze-v-user-guide/MicroBlaze-V-Architecture
The MicroBlaze™ V generic board in QEMU has following supported devices:
- timer
- uartlite
- uart16550
- emaclite
- timer2
- axi emac
- axi dma
The MicroBlaze™ V core in QEMU has the following configuration:
- RV32I base integer instruction set
- "Zicsr" Control and Status register instructions
- "Zifencei" instruction-fetch
- Extensions: m, a, f, c
Running
"""""""
Below is an example command line for launching mainline U-boot
(xilinx_mbv32_defconfig) on the Microblaze-V generic board.
.. code-block:: bash
$ qemu-system-riscv32 -M amd-microblaze-v-generic \
-display none \
-device loader,addr=0x80000000,file=u-boot-spl.bin,cpu-num=0 \
-device loader,addr=0x80200000,file=u-boot.img \
-serial mon:stdio \
-device loader,addr=0x83000000,file=system.dtb \
-m 2g

17
docs/system/riscv/virt.rst
View file

@ -94,6 +94,12 @@ command line:
$ qemu-system-riscv64 -M virt -device riscv-iommu-pci (...)
It also has support for the riscv-iommu-sys platform device:
.. code-block:: bash
$ qemu-system-riscv64 -M virt,iommu-sys=on (...)
Refer to :ref:`riscv-iommu` for more information on how the RISC-V IOMMU support
works.
@ -123,12 +129,23 @@ The following machine-specific options are supported:
MSIs. When not specified, this option is assumed to be "none" which selects
SiFive PLIC to handle wired interrupts.
This option also interacts with '-accel kvm'. When using "aia=aplic-imsic"
with KVM, it is possible to set the use of the kernel irqchip in split mode
by using "-accel kvm,kernel-irqchip=split". In this case the ``virt`` machine
will emulate the APLIC controller instead of using the APLIC controller from
the irqchip. See :ref:`riscv-aia` for more details on all available AIA
modes.
- aia-guests=nnn
The number of per-HART VS-level AIA IMSIC pages to be emulated for a guest
having AIA IMSIC (i.e. "aia=aplic-imsic" selected). When not specified,
the default number of per-HART VS-level AIA IMSIC pages is 0.
- iommu-sys=[on|off]
Enables the riscv-iommu-sys platform device. Defaults to 'off'.
Running Linux kernel
--------------------

1
docs/system/target-riscv.rst
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@ -66,6 +66,7 @@ undocumented; you can get a complete list by running
.. toctree::
:maxdepth: 1
riscv/microblaze-v-generic
riscv/microchip-icicle-kit
riscv/shakti-c
riscv/sifive_u