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apic: Store X86CPU in APICCommonState

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Prepares for using a link<> property to connect APIC with CPU and for
changing the CPU APIs to CPUState.

Resolve Coding Style warnings by moving the closing parenthesis of
foreach_apic() macro to next line.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
This commit is contained in:
Andreas Färber 2012-10-10 14:10:07 +02:00
parent 449994eb58
commit 60671e583c
5 changed files with 30 additions and 25 deletions
Download patch file Download diff file Expand all files Collapse all files

38
hw/apic.c
View file

@ -107,7 +107,7 @@ static void apic_sync_vapic(APICCommonState *s, int sync_type)
length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr);
if (sync_type & SYNC_TO_VAPIC) {
assert(qemu_cpu_is_self(s->cpu_env));
assert(qemu_cpu_is_self(&s->cpu->env));
vapic_state.tpr = s->tpr;
vapic_state.enabled = 1;
@ -151,15 +151,15 @@ static void apic_local_deliver(APICCommonState *s, int vector)
switch ((lvt >> 8) & 7) {
case APIC_DM_SMI:
cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI);
cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_SMI);
break;
case APIC_DM_NMI:
cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI);
cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_NMI);
break;
case APIC_DM_EXTINT:
cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
break;
case APIC_DM_FIXED:
@ -187,7 +187,7 @@ void apic_deliver_pic_intr(DeviceState *d, int level)
reset_bit(s->irr, lvt & 0xff);
/* fall through */
case APIC_DM_EXTINT:
cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
break;
}
}
@ -248,18 +248,22 @@ static void apic_bus_deliver(const uint32_t *deliver_bitmask,
case APIC_DM_SMI:
foreach_apic(apic_iter, deliver_bitmask,
cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
cpu_interrupt(&apic_iter->cpu->env, CPU_INTERRUPT_SMI)
);
return;
case APIC_DM_NMI:
foreach_apic(apic_iter, deliver_bitmask,
cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
cpu_interrupt(&apic_iter->cpu->env, CPU_INTERRUPT_NMI)
);
return;
case APIC_DM_INIT:
/* normal INIT IPI sent to processors */
foreach_apic(apic_iter, deliver_bitmask,
cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
cpu_interrupt(&apic_iter->cpu->env,
CPU_INTERRUPT_INIT)
);
return;
case APIC_DM_EXTINT:
@ -293,7 +297,7 @@ static void apic_set_base(APICCommonState *s, uint64_t val)
/* if disabled, cannot be enabled again */
if (!(val & MSR_IA32_APICBASE_ENABLE)) {
s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
cpu_clear_apic_feature(s->cpu_env);
cpu_clear_apic_feature(&s->cpu->env);
s->spurious_vec &= ~APIC_SV_ENABLE;
}
}
@ -362,10 +366,10 @@ static void apic_update_irq(APICCommonState *s)
if (!(s->spurious_vec & APIC_SV_ENABLE)) {
return;
}
if (!qemu_cpu_is_self(s->cpu_env)) {
cpu_interrupt(s->cpu_env, CPU_INTERRUPT_POLL);
if (!qemu_cpu_is_self(&s->cpu->env)) {
cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_POLL);
} else if (apic_irq_pending(s) > 0) {
cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
}
}
@ -472,18 +476,18 @@ static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
static void apic_startup(APICCommonState *s, int vector_num)
{
s->sipi_vector = vector_num;
cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_SIPI);
}
void apic_sipi(DeviceState *d)
{
APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_SIPI);
if (!s->wait_for_sipi)
return;
cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector);
cpu_x86_load_seg_cache_sipi(&s->cpu->env, s->sipi_vector);
s->wait_for_sipi = 0;
}
@ -672,7 +676,7 @@ static uint32_t apic_mem_readl(void *opaque, hwaddr addr)
case 0x08:
apic_sync_vapic(s, SYNC_FROM_VAPIC);
if (apic_report_tpr_access) {
cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_READ);
cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_READ);
}
val = s->tpr;
break;
@ -774,7 +778,7 @@ static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val)
break;
case 0x08:
if (apic_report_tpr_access) {
cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_WRITE);
cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_WRITE);
}
s->tpr = val;
apic_sync_vapic(s, SYNC_TO_VAPIC);