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spapr, xics, xive: Move SpaprIrq::post_load hook to backends

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The remaining logic in the post_load hook really belongs to the interrupt
controller backends, and just needs to be called on the active controller
(after the active controller is set to the right thing based on the
incoming migration in the generic spapr_irq_post_load() logic).

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
David Gibson 2019-09-27 10:53:53 +10:00
parent 567192d486
commit 605994e5b7
5 changed files with 21 additions and 46 deletions
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45
hw/ppc/spapr_irq.c
View file

@ -100,43 +100,22 @@ int spapr_irq_init_kvm(int (*fn)(SpaprInterruptController *, Error **),
* XICS IRQ backend.
*/
static int spapr_irq_post_load_xics(SpaprMachineState *spapr, int version_id)
{
if (!kvm_irqchip_in_kernel()) {
CPUState *cs;
CPU_FOREACH(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
icp_resend(spapr_cpu_state(cpu)->icp);
}
}
return 0;
}
SpaprIrq spapr_irq_xics = {
.nr_xirqs = SPAPR_NR_XIRQS,
.nr_msis = SPAPR_NR_MSIS,
.xics = true,
.xive = false,
.post_load = spapr_irq_post_load_xics,
};
/*
* XIVE IRQ backend.
*/
static int spapr_irq_post_load_xive(SpaprMachineState *spapr, int version_id)
{
return spapr_xive_post_load(spapr->xive, version_id);
}
SpaprIrq spapr_irq_xive = {
.nr_xirqs = SPAPR_NR_XIRQS,
.nr_msis = SPAPR_NR_MSIS,
.xics = false,
.xive = true,
.post_load = spapr_irq_post_load_xive,
};
/*
@ -148,21 +127,6 @@ SpaprIrq spapr_irq_xive = {
* activated after an extra machine reset.
*/
/*
* Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
* default.
*/
static SpaprIrq *spapr_irq_current(SpaprMachineState *spapr)
{
return spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT) ?
&spapr_irq_xive : &spapr_irq_xics;
}
static int spapr_irq_post_load_dual(SpaprMachineState *spapr, int version_id)
{
return spapr_irq_current(spapr)->post_load(spapr, version_id);
}
/*
* Define values in sync with the XIVE and XICS backend
*/
@ -171,8 +135,6 @@ SpaprIrq spapr_irq_dual = {
.nr_msis = SPAPR_NR_MSIS,
.xics = true,
.xive = true,
.post_load = spapr_irq_post_load_dual,
};
@ -447,8 +409,11 @@ qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq)
int spapr_irq_post_load(SpaprMachineState *spapr, int version_id)
{
SpaprInterruptControllerClass *sicc;
spapr_irq_update_active_intc(spapr);
return spapr->irq->post_load(spapr, version_id);
sicc = SPAPR_INTC_GET_CLASS(spapr->active_intc);
return sicc->post_load(spapr->active_intc, version_id);
}
void spapr_irq_reset(SpaprMachineState *spapr, Error **errp)
@ -589,8 +554,6 @@ SpaprIrq spapr_irq_xics_legacy = {
.nr_msis = SPAPR_IRQ_XICS_LEGACY_NR_XIRQS,
.xics = true,
.xive = false,
.post_load = spapr_irq_post_load_xics,
};
static void spapr_irq_register_types(void)