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hw/acpi: move typeinfo to the file end
do so to avoid not necessary forward declarations and place typeinfo registration at the file end where it's usually expected. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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parent
1a37eca107
commit
5fdae20cef
1 changed files with 46 additions and 46 deletions
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@ -466,52 +466,6 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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return s->smb.smbus;
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return s->smb.smbus;
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}
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}
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static Property piix4_pm_properties[] = {
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DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
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DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
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DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
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DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
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DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState,
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use_acpi_pci_hotplug, true),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void piix4_pm_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->no_hotplug = 1;
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k->init = piix4_pm_initfn;
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k->config_write = pm_write_config;
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
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k->revision = 0x03;
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k->class_id = PCI_CLASS_BRIDGE_OTHER;
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dc->desc = "PM";
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dc->vmsd = &vmstate_acpi;
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dc->props = piix4_pm_properties;
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/*
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* Reason: part of PIIX4 southbridge, needs to be wired up,
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* e.g. by mips_malta_init()
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*/
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dc->cannot_instantiate_with_device_add_yet = true;
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}
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static const TypeInfo piix4_pm_info = {
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.name = TYPE_PIIX4_PM,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PIIX4PMState),
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.class_init = piix4_pm_class_init,
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};
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static void piix4_pm_register_types(void)
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{
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type_register_static(&piix4_pm_info);
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}
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type_init(piix4_pm_register_types)
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static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
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static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
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{
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{
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PIIX4PMState *s = opaque;
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PIIX4PMState *s = opaque;
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@ -566,3 +520,49 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
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s->cpu_added_notifier.notify = piix4_cpu_added_req;
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s->cpu_added_notifier.notify = piix4_cpu_added_req;
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qemu_register_cpu_added_notifier(&s->cpu_added_notifier);
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qemu_register_cpu_added_notifier(&s->cpu_added_notifier);
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}
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}
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static Property piix4_pm_properties[] = {
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DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
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DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
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DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
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DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
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DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState,
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use_acpi_pci_hotplug, true),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void piix4_pm_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->no_hotplug = 1;
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k->init = piix4_pm_initfn;
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k->config_write = pm_write_config;
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
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k->revision = 0x03;
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k->class_id = PCI_CLASS_BRIDGE_OTHER;
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dc->desc = "PM";
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dc->vmsd = &vmstate_acpi;
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dc->props = piix4_pm_properties;
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/*
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* Reason: part of PIIX4 southbridge, needs to be wired up,
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* e.g. by mips_malta_init()
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*/
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dc->cannot_instantiate_with_device_add_yet = true;
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}
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static const TypeInfo piix4_pm_info = {
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.name = TYPE_PIIX4_PM,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PIIX4PMState),
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.class_init = piix4_pm_class_init,
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};
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static void piix4_pm_register_types(void)
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{
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type_register_static(&piix4_pm_info);
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}
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type_init(piix4_pm_register_types)
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