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target/ppc: Remove id_tlbs flag from CPU env

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This flag for split instruction/data TLBs is only set for 6xx soft TLB
MMU model and not used otherwise so no need to have a separate flag
for that.

Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
BALATON Zoltan 2024-05-13 01:28:02 +02:00 • committed by Nicholas Piggin
parent 306b532030
commit 5fd257f599
6 changed files with 14 additions and 35 deletions
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5
target/ppc/cpu.h
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@ -1281,7 +1281,6 @@ struct CPUArchState {
int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
int nb_ways; /* Number of ways in the TLB set */
int last_way; /* Last used way used to allocate TLB in a LRU way */
int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
int nb_pids; /* Number of available PID registers */
int tlb_type; /* Type of TLB we're dealing with */
ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
@ -2897,6 +2896,10 @@ static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
}
static inline bool ppc_is_split_tlb(PowerPCCPU *cpu)
{
return cpu->env.tlb_type == TLB_6XX;
}
#endif
static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)