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https://github.com/Motorhead1991/qemu.git
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target-arm queue:
* hw/intc/arm_gicv3: fix wrong values when reading IPRIORITYR * target/arm: fix read of freed memory in kvm_arm_machine_init_done() * virt: support up to 512 CPUs * virt: support 256MB ECAM PCI region (for more PCI devices) * xlnx-zynqmp: Use Cortex-R5F, not Cortex-R5 * mps2-tz: Implement and use the TrustZone Memory Protection Controller * target/arm: enforce alignment checking for v6M cores * xen: Don't use memory_region_init_ram_nomigrate() in pci_assign_dev_load_option_rom() * vl.c: Don't zero-initialize statics for serial_hds -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJbLPHgAAoJEDwlJe0UNgzeCugP/0yFWNkIQqgPX1D2fDLaea8z fj2QCkMHVDC/iM9s2Q7PpQDwfxMfE5MbvcavyfcVWe6lthyWQvvQ+5j4JHipgEup vdGX+ASA9sbC3kJ1u/OUekz6JliEWaxOyImnj2gyQfBw8zuMfiF+eTmtoKXcJC3u KNSNvArPIaFLNKsaQgTQE19Bu8CxIzfGEzsIgeAoD4gE7wv48EWqpOaYdIkbDo+0 gJylBVCa46pmf56ESCuLTDZC+2FxBcw+uCFtD5zzt6YVV0Fli1ja9FNwLP17YHqg GOfNQ6melPeNUF+ByIEaPLWrq+Sy2P6wlnVlvKcKis8nXq497VjJdvv1txbbnyrn s4dKgVHjQP6EocvaVKCxXsLfjvPUCF2+f/uIdA8IR4WRilgTEfV3IdOYNuKjOFXb FcYap5UrX4ikEBkDBIBkh1BQXqOAU+lf8JjW1O6kn8PbfkEu2oRqGybWtEOjr+mz +iNsJ+4PydJ34WlvPKkzDG7GjEJcleStmgD3/DdL3r+jtjBYBT97xOAqWVnyVRYb NEUQEGmG894THftieuMw6r8vi4u24ZkI/3vGvBeSZ1od8IFEjzENRWkhYoDhLO5r LH16da19pVgWnLSXJnhxLTRaYNNAphNSIW30GDAwMbuXFK+LpCBufT8X7b6RerNx tOYET9DwlQRYEiuBVeSk =1T5q -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180622' into staging target-arm queue: * hw/intc/arm_gicv3: fix wrong values when reading IPRIORITYR * target/arm: fix read of freed memory in kvm_arm_machine_init_done() * virt: support up to 512 CPUs * virt: support 256MB ECAM PCI region (for more PCI devices) * xlnx-zynqmp: Use Cortex-R5F, not Cortex-R5 * mps2-tz: Implement and use the TrustZone Memory Protection Controller * target/arm: enforce alignment checking for v6M cores * xen: Don't use memory_region_init_ram_nomigrate() in pci_assign_dev_load_option_rom() * vl.c: Don't zero-initialize statics for serial_hds # gpg: Signature made Fri 22 Jun 2018 13:56:00 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180622: (28 commits) xen: Don't use memory_region_init_ram_nomigrate() in pci_assign_dev_load_option_rom() vl.c: Don't zero-initialize statics for serial_hds target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline target/arm: Introduce ARM_FEATURE_M_MAIN hw/arm/mps2-tz.c: Instantiate MPCs hw/arm/iotkit: Wire up MPC interrupt lines hw/arm/iotkit: Instantiate MPC hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUS hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate hw/misc/tz-mpc.c: Implement correct blocked-access behaviour hw/misc/tz-mpc.c: Implement registers hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller xlnx-zynqmp: Swap Cortex-R5 for Cortex-R5F target-arm: Add the Cortex-R5F hw/arm/virt: Increase max_cpus to 512 hw/arm/virt: Use 256MB ECAM region by default hw/arm/virt: Add virt-3.0 machine type hw/arm/virt: Add a new 256MB ECAM region hw/arm/virt: Register two redistributor regions when necessary hw/arm/virt-acpi-build: Advertise one or two GICR structures ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
5fce312200
48 changed files with 1250 additions and 111 deletions
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@ -42,6 +42,9 @@
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* + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
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* + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
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* + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
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* Controlling each of the 16 expansion MPCs which a system using the IoTKit
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* might provide:
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* + named GPIO inputs mpcexp_status[0..15]
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*/
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#ifndef IOTKIT_H
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@ -51,6 +54,7 @@
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#include "hw/arm/armv7m.h"
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#include "hw/misc/iotkit-secctl.h"
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#include "hw/misc/tz-ppc.h"
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#include "hw/misc/tz-mpc.h"
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#include "hw/timer/cmsdk-apb-timer.h"
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#include "hw/misc/unimp.h"
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#include "hw/or-irq.h"
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@ -74,11 +78,14 @@ typedef struct IoTKit {
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IoTKitSecCtl secctl;
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TZPPC apb_ppc0;
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TZPPC apb_ppc1;
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TZMPC mpc;
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CMSDKAPBTIMER timer0;
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CMSDKAPBTIMER timer1;
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qemu_or_irq ppc_irq_orgate;
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SplitIRQ sec_resp_splitter;
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SplitIRQ ppc_irq_splitter[NUM_PPCS];
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SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC];
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qemu_or_irq mpc_irq_orgate;
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UnimplementedDeviceState dualtimer;
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UnimplementedDeviceState s32ktimer;
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@ -97,6 +104,7 @@ typedef struct IoTKit {
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qemu_irq nsc_cfg_in;
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qemu_irq irq_status_in[NUM_EXTERNAL_PPCS];
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qemu_irq mpcexp_status_in[IOTS_NUM_EXP_MPC];
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uint32_t nsccfg;
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@ -35,6 +35,8 @@
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#include "qemu/notify.h"
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#include "hw/boards.h"
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#include "hw/arm/arm.h"
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#include "sysemu/kvm.h"
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#include "hw/intc/arm_gicv3_common.h"
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#define NUM_GICV2M_SPIS 64
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#define NUM_VIRTIO_TRANSPORTS 32
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@ -60,6 +62,7 @@ enum {
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VIRT_GIC_V2M,
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VIRT_GIC_ITS,
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VIRT_GIC_REDIST,
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VIRT_GIC_REDIST2,
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VIRT_SMMU,
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VIRT_UART,
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VIRT_MMIO,
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@ -69,6 +72,7 @@ enum {
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VIRT_PCIE_MMIO,
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VIRT_PCIE_PIO,
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VIRT_PCIE_ECAM,
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VIRT_PCIE_ECAM_HIGH,
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VIRT_PLATFORM_BUS,
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VIRT_PCIE_MMIO_HIGH,
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VIRT_GPIO,
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@ -94,6 +98,7 @@ typedef struct {
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bool no_pmu;
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bool claim_edge_triggered_timers;
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bool smbios_old_sys_ver;
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bool no_highmem_ecam;
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} VirtMachineClass;
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typedef struct {
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@ -103,6 +108,7 @@ typedef struct {
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FWCfgState *fw_cfg;
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bool secure;
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bool highmem;
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bool highmem_ecam;
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bool its;
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bool virt;
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int32_t gic_version;
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@ -120,6 +126,8 @@ typedef struct {
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int psci_conduit;
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} VirtMachineState;
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#define VIRT_ECAM_ID(high) (high ? VIRT_PCIE_ECAM_HIGH : VIRT_PCIE_ECAM)
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#define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
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#define VIRT_MACHINE(obj) \
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OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE)
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@ -130,4 +138,15 @@ typedef struct {
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void virt_acpi_setup(VirtMachineState *vms);
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/* Return the number of used redistributor regions */
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static inline int virt_gicv3_redist_region_count(VirtMachineState *vms)
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{
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uint32_t redist0_capacity =
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vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
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assert(vms->gic_version == 3);
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return vms->smp_cpus > redist0_capacity ? 2 : 1;
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}
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#endif /* QEMU_ARM_VIRT_H */
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@ -35,6 +35,8 @@
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#define GICV3_MAXIRQ 1020
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#define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL)
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#define GICV3_REDIST_SIZE 0x20000
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/* Number of SGI target-list bits */
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#define GICV3_TARGETLIST_BITS 16
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@ -210,7 +212,9 @@ struct GICv3State {
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/*< public >*/
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MemoryRegion iomem_dist; /* Distributor */
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MemoryRegion iomem_redist; /* Redistributors */
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MemoryRegion *iomem_redist; /* Redistributor Regions */
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uint32_t *redist_region_count; /* redistributor count within each region */
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uint32_t nb_redist_regions; /* number of redist regions */
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uint32_t num_cpu;
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uint32_t num_irq;
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@ -292,6 +296,6 @@ typedef struct ARMGICv3CommonClass {
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} ARMGICv3CommonClass;
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void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
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const MemoryRegionOps *ops);
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const MemoryRegionOps *ops, Error **errp);
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#endif
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@ -39,6 +39,11 @@
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* + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
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* + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
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* + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
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* Controlling the MPC in the IoTKit:
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* + named GPIO input mpc_status
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* Controlling each of the 16 expansion MPCs which a system using the IoTKit
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* might provide:
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* + named GPIO inputs mpcexp_status[0..15]
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*/
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#ifndef IOTKIT_SECCTL_H
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@ -55,6 +60,8 @@
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#define IOTS_NUM_APB_PPC 2
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#define IOTS_NUM_APB_EXP_PPC 4
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#define IOTS_NUM_AHB_EXP_PPC 4
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#define IOTS_NUM_EXP_MPC 16
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#define IOTS_NUM_MPC 1
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typedef struct IoTKitSecCtl IoTKitSecCtl;
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uint32_t secrespcfg;
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uint32_t nsccfg;
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uint32_t brginten;
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uint32_t mpcintstatus;
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IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC];
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IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC];
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80
include/hw/misc/tz-mpc.h
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80
include/hw/misc/tz-mpc.h
Normal file
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@ -0,0 +1,80 @@
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/*
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* ARM AHB5 TrustZone Memory Protection Controller emulation
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/* This is a model of the TrustZone memory protection controller (MPC).
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* It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM
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* (DDI 0571G):
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* https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g
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*
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* The MPC sits in front of memory and allows secure software to
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* configure it to either pass through or reject transactions.
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* Rejected transactions may be configured to either be aborted, or to
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* behave as RAZ/WI. An interrupt can be signalled for a rejected transaction.
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*
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* The MPC has a register interface which the guest uses to configure it.
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*
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* QEMU interface:
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* + sysbus MMIO region 0: MemoryRegion for the MPC's config registers
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* + sysbus MMIO region 1: MemoryRegion for the upstream end of the MPC
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* + Property "downstream": MemoryRegion defining the downstream memory
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* + Named GPIO output "irq": set for a transaction-failed interrupt
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*/
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#ifndef TZ_MPC_H
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#define TZ_MPC_H
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#include "hw/sysbus.h"
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#define TYPE_TZ_MPC "tz-mpc"
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#define TZ_MPC(obj) OBJECT_CHECK(TZMPC, (obj), TYPE_TZ_MPC)
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#define TZ_NUM_PORTS 16
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#define TYPE_TZ_MPC_IOMMU_MEMORY_REGION "tz-mpc-iommu-memory-region"
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typedef struct TZMPC TZMPC;
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struct TZMPC {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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/* State */
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uint32_t ctrl;
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uint32_t blk_idx;
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uint32_t int_stat;
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uint32_t int_en;
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uint32_t int_info1;
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uint32_t int_info2;
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uint32_t *blk_lut;
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qemu_irq irq;
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/* Properties */
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MemoryRegion *downstream;
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hwaddr blocksize;
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uint32_t blk_max;
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/* MemoryRegions exposed to user */
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MemoryRegion regmr;
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IOMMUMemoryRegion upstream;
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/* MemoryRegion used internally */
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MemoryRegion blocked_io;
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AddressSpace downstream_as;
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AddressSpace blocked_io_as;
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};
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#endif
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