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target/sparc: Move SLL, SRL, SRA to decodetree

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Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-02 14:48:10 -07:00
parent a9aba13dae
commit 5fc546ee35
2 changed files with 92 additions and 104 deletions
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14
target/sparc/insns.decode
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@ -183,6 +183,20 @@ TSUBcc 10 ..... 100001 ..... . ............. @r_r_ri_cc1
TADDccTV 10 ..... 100010 ..... . ............. @r_r_ri_cc1
TSUBccTV 10 ..... 100011 ..... . ............. @r_r_ri_cc1
&shiftr rd rs1 rs2 x:bool
@shiftr .. rd:5 ...... rs1:5 . x:1 ....... rs2:5 &shiftr
SLL_r 10 ..... 100101 ..... 0 . 0000000 ..... @shiftr
SRL_r 10 ..... 100110 ..... 0 . 0000000 ..... @shiftr
SRA_r 10 ..... 100111 ..... 0 . 0000000 ..... @shiftr
&shifti rd rs1 i x:bool
@shifti .. rd:5 ...... rs1:5 . x:1 ...... i:6 &shifti
SLL_i 10 ..... 100101 ..... 1 . 000000 ...... @shifti
SRL_i 10 ..... 100110 ..... 1 . 000000 ...... @shifti
SRA_i 10 ..... 100111 ..... 1 . 000000 ...... @shifti
Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
{
# For v7, the entire simm13 field is present, but masked to 7 bits.