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target/mips: Provide R/W access to SAARI and SAAR CP0 registers

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Provide R/W access to SAARI and SAAR CP0 registers.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
This commit is contained in:
Yongbok Kim 2019-01-03 14:58:16 +01:00 • committed by Aleksandar Markovic
parent 167db30e98
commit 5fb2dcd179
5 changed files with 120 additions and 4 deletions
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target/mips/internal.h
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@ -61,6 +61,7 @@ struct mips_def_t {
target_ulong CP0_EBaseWG_rw_bitmask;
uint64_t insn_flags;
enum mips_mmu_types mmu_type;
int32_t SAARP;
};
extern const struct mips_def_t mips_defs[];