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find -type f | xargs sed -i 's/[\t ]$//g' # on most files

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-09-16 21:08:06 +00:00
parent bd494f4cbd
commit 5fafdf24ef
327 changed files with 4737 additions and 4738 deletions
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12
target-arm/cpu.h
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@ -1,6 +1,6 @@
/*
* ARM virtual CPU header
*
*
* Copyright (c) 2003 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
@ -64,11 +64,11 @@ typedef struct CPUARMState {
uint32_t banked_spsr[6];
uint32_t banked_r13[6];
uint32_t banked_r14[6];
/* These hold r8-r12. */
uint32_t usr_regs[5];
uint32_t fiq_regs[5];
/* cpsr flag cache for faster execution */
uint32_t CF; /* 0 or 1 */
uint32_t VF; /* V is the bit 31. All other bits are undefined */
@ -134,7 +134,7 @@ typedef struct CPUARMState {
/* Temporary variables if we don't have spare fp regs. */
float32 tmp0s, tmp1s;
float64 tmp0d, tmp1d;
float_status fp_status;
} vfp;
@ -171,7 +171,7 @@ void switch_mode(CPUARMState *, int);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
int cpu_arm_signal_handler(int host_signum, void *pinfo,
int cpu_arm_signal_handler(int host_signum, void *pinfo,
void *puc);
#define CPSR_M (0x1f)
@ -193,7 +193,7 @@ static inline uint32_t cpsr_read(CPUARMState *env)
{
int ZF;
ZF = (env->NZF == 0);
return env->uncached_cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
return env->uncached_cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
(env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
| (env->thumb << 5);
}