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find -type f | xargs sed -i 's/[\t ]$//g' # on most files
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths
parent
bd494f4cbd
commit
5fafdf24ef
327 changed files with 4737 additions and 4738 deletions
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@ -1,8 +1,8 @@
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/*
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* USB UHCI controller emulation
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*
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*
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* Copyright (c) 2005 Fabrice Bellard
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*
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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@ -84,7 +84,7 @@ typedef struct UHCIState {
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/* For simplicity of implementation we only allow a single pending USB
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request. This means all usb traffic on this controller is effectively
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suspended until that transfer completes. When the transfer completes
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the next transfer from that queue will be processed. However
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the next transfer from that queue will be processed. However
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other queues will not be processed until the next frame. The solution
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is to allow multiple pending requests. */
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uint32_t async_qh;
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@ -149,7 +149,7 @@ static void uhci_reset(UHCIState *s)
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static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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UHCIState *s = opaque;
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addr &= 0x1f;
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switch(addr) {
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case 0x0c:
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@ -178,7 +178,7 @@ static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr)
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static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
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{
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UHCIState *s = opaque;
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addr &= 0x1f;
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#ifdef DEBUG
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printf("uhci writew port=0x%04x val=0x%04x\n", addr, val);
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@ -243,7 +243,7 @@ static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
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dev = port->port.dev;
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if (dev) {
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/* port reset */
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if ( (val & UHCI_PORT_RESET) &&
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if ( (val & UHCI_PORT_RESET) &&
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!(port->ctrl & UHCI_PORT_RESET) ) {
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usb_send_msg(dev, USB_MSG_RESET);
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}
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@ -280,7 +280,7 @@ static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr)
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UHCIPort *port;
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int n;
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n = (addr >> 1) & 7;
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if (n >= NB_PORTS)
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if (n >= NB_PORTS)
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goto read_default;
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port = &s->ports[n];
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val = port->ctrl;
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@ -458,7 +458,7 @@ static int uhci_handle_td(UHCIState *s, UHCI_TD *td, int *int_mask)
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if (td->ctrl & TD_CTRL_IOC) {
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*int_mask |= 0x01;
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}
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if (!(td->ctrl & TD_CTRL_ACTIVE))
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return 1;
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@ -530,7 +530,7 @@ static int uhci_handle_td(UHCIState *s, UHCI_TD *td, int *int_mask)
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here. The docs are somewhat unclear, but win2k relies on this
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behavior. */
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td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK);
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if (pid == USB_TOKEN_IN &&
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if (pid == USB_TOKEN_IN &&
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(td->ctrl & TD_CTRL_SPD) &&
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len < max_len) {
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*int_mask |= 0x02;
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@ -555,7 +555,7 @@ static int uhci_handle_td(UHCIState *s, UHCI_TD *td, int *int_mask)
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uhci_update_irq(s);
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}
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}
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td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
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td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
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(err << TD_CTRL_ERROR_SHIFT);
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return 1;
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case USB_RET_NAK:
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@ -597,7 +597,7 @@ static void uhci_async_complete_packet(USBPacket * packet, void *opaque)
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le32_to_cpus(&qh.el_link);
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/* Re-process the queue containing the async packet. */
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while (1) {
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cpu_physical_memory_read(qh.el_link & ~0xf,
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cpu_physical_memory_read(qh.el_link & ~0xf,
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(uint8_t *)&td, sizeof(td));
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le32_to_cpus(&td.link);
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le32_to_cpus(&td.ctrl);
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@ -608,8 +608,8 @@ static void uhci_async_complete_packet(USBPacket * packet, void *opaque)
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/* update the status bits of the TD */
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if (old_td_ctrl != td.ctrl) {
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val = cpu_to_le32(td.ctrl);
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cpu_physical_memory_write((qh.el_link & ~0xf) + 4,
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(const uint8_t *)&val,
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cpu_physical_memory_write((qh.el_link & ~0xf) + 4,
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(const uint8_t *)&val,
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sizeof(val));
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}
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if (ret < 0)
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@ -621,8 +621,8 @@ static void uhci_async_complete_packet(USBPacket * packet, void *opaque)
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/* update qh element link */
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qh.el_link = td.link;
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val = cpu_to_le32(qh.el_link);
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cpu_physical_memory_write((link & ~0xf) + 4,
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(const uint8_t *)&val,
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cpu_physical_memory_write((link & ~0xf) + 4,
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(const uint8_t *)&val,
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sizeof(val));
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if (!(qh.el_link & 4))
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break;
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@ -690,7 +690,7 @@ static void uhci_frame_timer(void *opaque)
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/* TD */
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if (--cnt == 0)
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break;
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cpu_physical_memory_read(qh.el_link & ~0xf,
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cpu_physical_memory_read(qh.el_link & ~0xf,
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(uint8_t *)&td, sizeof(td));
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le32_to_cpus(&td.link);
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le32_to_cpus(&td.ctrl);
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@ -701,8 +701,8 @@ static void uhci_frame_timer(void *opaque)
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/* update the status bits of the TD */
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if (old_td_ctrl != td.ctrl) {
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val = cpu_to_le32(td.ctrl);
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cpu_physical_memory_write((qh.el_link & ~0xf) + 4,
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(const uint8_t *)&val,
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cpu_physical_memory_write((qh.el_link & ~0xf) + 4,
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(const uint8_t *)&val,
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sizeof(val));
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}
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if (ret < 0)
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@ -713,8 +713,8 @@ static void uhci_frame_timer(void *opaque)
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/* update qh element link */
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qh.el_link = td.link;
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val = cpu_to_le32(qh.el_link);
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cpu_physical_memory_write((link & ~0xf) + 4,
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(const uint8_t *)&val,
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cpu_physical_memory_write((link & ~0xf) + 4,
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(const uint8_t *)&val,
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sizeof(val));
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if (qh.el_link & 4) {
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/* depth first */
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@ -740,8 +740,8 @@ static void uhci_frame_timer(void *opaque)
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/* update the status bits of the TD */
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if (old_td_ctrl != td.ctrl) {
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val = cpu_to_le32(td.ctrl);
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cpu_physical_memory_write((link & ~0xf) + 4,
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(const uint8_t *)&val,
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cpu_physical_memory_write((link & ~0xf) + 4,
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(const uint8_t *)&val,
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sizeof(val));
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}
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if (ret < 0)
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@ -768,12 +768,12 @@ static void uhci_frame_timer(void *opaque)
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s->async_qh = 0;
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}
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/* prepare the timer for the next frame */
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expire_time = qemu_get_clock(vm_clock) +
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expire_time = qemu_get_clock(vm_clock) +
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(ticks_per_sec / FRAME_TIMER_FREQ);
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qemu_mod_timer(s->frame_timer, expire_time);
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}
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static void uhci_map(PCIDevice *pci_dev, int region_num,
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static void uhci_map(PCIDevice *pci_dev, int region_num,
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uint32_t addr, uint32_t size, int type)
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{
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UHCIState *s = (UHCIState *)pci_dev;
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@ -807,7 +807,7 @@ void usb_uhci_piix3_init(PCIBus *bus, int devfn)
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pci_conf[0x0e] = 0x00; // header_type
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pci_conf[0x3d] = 4; // interrupt pin 3
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pci_conf[0x60] = 0x10; // release number
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for(i = 0; i < NB_PORTS; i++) {
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qemu_register_usb_port(&s->ports[i].port, s, i, uhci_attach);
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}
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@ -817,7 +817,7 @@ void usb_uhci_piix3_init(PCIBus *bus, int devfn)
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/* Use region 4 for consistency with real hardware. BSD guests seem
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to rely on this. */
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pci_register_io_region(&s->dev, 4, 0x20,
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pci_register_io_region(&s->dev, 4, 0x20,
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PCI_ADDRESS_SPACE_IO, uhci_map);
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}
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