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tcg: Convert bswap16 to TCGOutOpBswap

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Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-10 18:32:08 -08:00
parent e579c717cb
commit 5fa8e13872
24 changed files with 235 additions and 210 deletions
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2
tcg/mips/tcg-target-has.h
View file

@ -39,7 +39,6 @@ extern bool use_mips32r2_instructions;
#endif
/* optional instructions */
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
#if TCG_TARGET_REG_BITS == 64
@ -57,7 +56,6 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_qemu_st8_i32 0
#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_bswap16_i64 1
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_extract2_i64 0

74
tcg/mips/tcg-target.c.inc
View file

@ -702,39 +702,6 @@ static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
g_assert_not_reached();
}
static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
{
/* ret and arg can't be register tmp0 */
tcg_debug_assert(ret != TCG_TMP0);
tcg_debug_assert(arg != TCG_TMP0);
/* With arg = abcd: */
if (use_mips32r2_instructions) {
tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */
if (flags & TCG_BSWAP_OS) {
tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */
} else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */
}
return;
}
tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */
if (!(flags & TCG_BSWAP_IZ)) {
tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */
}
if (flags & TCG_BSWAP_OS) {
tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */
tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */
} else {
tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */
if (flags & TCG_BSWAP_OZ) {
tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */
}
}
tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */
}
static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub)
{
if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) {
@ -2168,6 +2135,41 @@ static const TCGOutOpBinary outop_xor = {
.out_rri = tgen_xori,
};
static void tgen_bswap16(TCGContext *s, TCGType type,
TCGReg ret, TCGReg arg, unsigned flags)
{
/* With arg = abcd: */
if (use_mips32r2_instructions) {
tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */
if (flags & TCG_BSWAP_OS) {
tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */
} else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */
}
return;
}
tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */
if (!(flags & TCG_BSWAP_IZ)) {
tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */
}
if (flags & TCG_BSWAP_OS) {
tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */
tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */
} else {
tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */
if (flags & TCG_BSWAP_OZ) {
tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */
}
}
tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */
}
static const TCGOutOpBswap outop_bswap16 = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_bswap16,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_sub(s, type, a0, TCG_REG_ZERO, a1);
@ -2259,10 +2261,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_ldst(s, i1, a0, a1, a2);
break;
case INDEX_op_bswap16_i32:
case INDEX_op_bswap16_i64:
tcg_out_bswap16(s, a0, a1, a2);
break;
case INDEX_op_bswap32_i32:
tcg_out_bswap32(s, a0, a1, 0);
break;
@ -2373,7 +2371,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld16u_i32:
case INDEX_op_ld16s_i32:
case INDEX_op_ld_i32:
case INDEX_op_bswap16_i32:
case INDEX_op_bswap32_i32:
case INDEX_op_extract_i32:
case INDEX_op_sextract_i32:
@ -2384,7 +2381,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld32s_i64:
case INDEX_op_ld32u_i64:
case INDEX_op_ld_i64:
case INDEX_op_bswap16_i64:
case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64:
case INDEX_op_ext_i32_i64: