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https://github.com/Motorhead1991/qemu.git
synced 2025-08-07 09:43:56 -06:00
Compile pflash_cfi02 only once
Push TARGET_WORDS_BIGENDIAN dependency to board level. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl
parent
53b67b3052
commit
5f9fc5ad7e
12 changed files with 157 additions and 77 deletions
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@ -103,7 +103,8 @@ static void pflash_timer (void *opaque)
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pfl->cmd = 0;
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}
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static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset, int width)
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static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
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int width, int be)
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{
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target_phys_addr_t boff;
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uint32_t ret;
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@ -140,27 +141,27 @@ static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset, int width
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// DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
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break;
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case 2:
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#if defined(TARGET_WORDS_BIGENDIAN)
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ret = p[offset] << 8;
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ret |= p[offset + 1];
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#else
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ret = p[offset];
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ret |= p[offset + 1] << 8;
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#endif
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if (be) {
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ret = p[offset] << 8;
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ret |= p[offset + 1];
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} else {
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ret = p[offset];
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ret |= p[offset + 1] << 8;
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}
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// DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
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break;
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case 4:
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#if defined(TARGET_WORDS_BIGENDIAN)
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ret = p[offset] << 24;
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ret |= p[offset + 1] << 16;
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ret |= p[offset + 2] << 8;
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ret |= p[offset + 3];
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#else
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ret = p[offset];
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ret |= p[offset + 1] << 8;
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ret |= p[offset + 2] << 16;
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ret |= p[offset + 3] << 24;
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#endif
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if (be) {
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ret = p[offset] << 24;
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ret |= p[offset + 1] << 16;
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ret |= p[offset + 2] << 8;
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ret |= p[offset + 3];
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} else {
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ret = p[offset];
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ret |= p[offset + 1] << 8;
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ret |= p[offset + 2] << 16;
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ret |= p[offset + 3] << 24;
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}
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// DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
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break;
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}
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@ -223,7 +224,7 @@ static void pflash_update(pflash_t *pfl, int offset,
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}
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static void pflash_write (pflash_t *pfl, target_phys_addr_t offset,
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uint32_t value, int width)
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uint32_t value, int width, int be)
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{
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target_phys_addr_t boff;
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uint8_t *p;
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@ -316,27 +317,27 @@ static void pflash_write (pflash_t *pfl, target_phys_addr_t offset,
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pflash_update(pfl, offset, 1);
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break;
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case 2:
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#if defined(TARGET_WORDS_BIGENDIAN)
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p[offset] &= value >> 8;
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p[offset + 1] &= value;
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#else
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p[offset] &= value;
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p[offset + 1] &= value >> 8;
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#endif
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if (be) {
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p[offset] &= value >> 8;
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p[offset + 1] &= value;
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} else {
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p[offset] &= value;
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p[offset + 1] &= value >> 8;
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}
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pflash_update(pfl, offset, 2);
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break;
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case 4:
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#if defined(TARGET_WORDS_BIGENDIAN)
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p[offset] &= value >> 24;
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p[offset + 1] &= value >> 16;
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p[offset + 2] &= value >> 8;
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p[offset + 3] &= value;
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#else
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p[offset] &= value;
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p[offset + 1] &= value >> 8;
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p[offset + 2] &= value >> 16;
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p[offset + 3] &= value >> 24;
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#endif
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if (be) {
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p[offset] &= value >> 24;
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p[offset + 1] &= value >> 16;
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p[offset + 2] &= value >> 8;
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p[offset + 3] &= value;
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} else {
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p[offset] &= value;
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p[offset + 1] &= value >> 8;
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p[offset + 2] &= value >> 16;
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p[offset + 3] &= value >> 24;
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}
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pflash_update(pfl, offset, 4);
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break;
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}
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@ -451,57 +452,110 @@ static void pflash_write (pflash_t *pfl, target_phys_addr_t offset,
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}
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static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr)
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static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr)
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{
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return pflash_read(opaque, addr, 1);
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return pflash_read(opaque, addr, 1, 1);
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}
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static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr)
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static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr)
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{
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return pflash_read(opaque, addr, 1, 0);
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}
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static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr)
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{
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pflash_t *pfl = opaque;
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return pflash_read(pfl, addr, 2);
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return pflash_read(pfl, addr, 2, 1);
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}
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static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr)
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static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr)
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{
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pflash_t *pfl = opaque;
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return pflash_read(pfl, addr, 4);
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return pflash_read(pfl, addr, 2, 0);
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}
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static void pflash_writeb (void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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pflash_write(opaque, addr, value, 1);
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}
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static void pflash_writew (void *opaque, target_phys_addr_t addr,
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uint32_t value)
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static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr)
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{
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pflash_t *pfl = opaque;
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pflash_write(pfl, addr, value, 2);
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return pflash_read(pfl, addr, 4, 1);
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}
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static void pflash_writel (void *opaque, target_phys_addr_t addr,
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uint32_t value)
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static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr)
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{
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pflash_t *pfl = opaque;
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pflash_write(pfl, addr, value, 4);
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return pflash_read(pfl, addr, 4, 0);
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}
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static CPUWriteMemoryFunc * const pflash_write_ops[] = {
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&pflash_writeb,
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&pflash_writew,
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&pflash_writel,
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static void pflash_writeb_be(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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pflash_write(opaque, addr, value, 1, 1);
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}
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static void pflash_writeb_le(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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pflash_write(opaque, addr, value, 1, 0);
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}
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static void pflash_writew_be(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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pflash_t *pfl = opaque;
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pflash_write(pfl, addr, value, 2, 1);
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}
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static void pflash_writew_le(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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pflash_t *pfl = opaque;
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pflash_write(pfl, addr, value, 2, 0);
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}
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static void pflash_writel_be(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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pflash_t *pfl = opaque;
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pflash_write(pfl, addr, value, 4, 1);
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}
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static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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pflash_t *pfl = opaque;
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pflash_write(pfl, addr, value, 4, 0);
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}
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static CPUWriteMemoryFunc * const pflash_write_ops_be[] = {
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&pflash_writeb_be,
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&pflash_writew_be,
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&pflash_writel_be,
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};
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static CPUReadMemoryFunc * const pflash_read_ops[] = {
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&pflash_readb,
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&pflash_readw,
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&pflash_readl,
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static CPUReadMemoryFunc * const pflash_read_ops_be[] = {
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&pflash_readb_be,
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&pflash_readw_be,
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&pflash_readl_be,
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};
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static CPUWriteMemoryFunc * const pflash_write_ops_le[] = {
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&pflash_writeb_le,
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&pflash_writew_le,
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&pflash_writel_le,
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};
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static CPUReadMemoryFunc * const pflash_read_ops_le[] = {
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&pflash_readb_le,
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&pflash_readw_le,
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&pflash_readl_le,
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};
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/* Count trailing zeroes of a 32 bits quantity */
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@ -543,7 +597,8 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
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int nb_blocs, int nb_mappings, int width,
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uint16_t id0, uint16_t id1,
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uint16_t id2, uint16_t id3,
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uint16_t unlock_addr0, uint16_t unlock_addr1)
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uint16_t unlock_addr0, uint16_t unlock_addr1,
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int be)
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{
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pflash_t *pfl;
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int32_t chip_len;
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@ -559,8 +614,15 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
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pfl = qemu_mallocz(sizeof(pflash_t));
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/* FIXME: Allocate ram ourselves. */
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pfl->storage = qemu_get_ram_ptr(off);
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pfl->fl_mem = cpu_register_io_memory(pflash_read_ops, pflash_write_ops,
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pfl);
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if (be) {
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pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be,
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pflash_write_ops_be,
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pfl);
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} else {
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pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le,
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pflash_write_ops_le,
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pfl);
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}
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pfl->off = off;
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pfl->base = base;
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pfl->chip_len = chip_len;
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