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target/xtensa: make internal MMU functions static

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Remove declarations of the internal mmu_helper functions from the cpu.h,
make these functions static and shuffle them.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2019-03-14 22:41:39 -07:00
parent 59419607fb
commit 5f7f36d07e
2 changed files with 87 additions and 95 deletions
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19
target/xtensa/cpu.h
View file

@ -658,17 +658,6 @@ static inline int xtensa_get_cring(const CPUXtensaState *env)
} }
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env,
bool dtlb, uint32_t way);
void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
uint32_t *vpn, uint32_t wi, uint32_t *ei);
int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
uint32_t *pwi, uint32_t *pei, uint8_t *pring);
void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
xtensa_tlb_entry *entry, bool dtlb,
unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
uint32_t vaddr, int is_write, int mmu_idx, uint32_t vaddr, int is_write, int mmu_idx,
uint32_t *paddr, uint32_t *page_size, unsigned *access); uint32_t *paddr, uint32_t *page_size, unsigned *access);
@ -679,14 +668,6 @@ static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env)
{ {
return env->system_er; return env->system_er;
} }
static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
bool dtlb, unsigned wi, unsigned ei)
{
return dtlb ?
env->dtlb[wi] + ei :
env->itlb[wi] + ei;
}
#endif #endif
static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env) static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)

153
target/xtensa/mmu_helper.c
View file

@ -78,7 +78,7 @@ static uint32_t get_page_size(const CPUXtensaState *env,
/*! /*!
* Get bit mask for the virtual address bits translated by the TLB way * Get bit mask for the virtual address bits translated by the TLB way
*/ */
uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, static uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env,
bool dtlb, uint32_t way) bool dtlb, uint32_t way)
{ {
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
@ -145,8 +145,9 @@ static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
* Split virtual address into VPN (with index) and entry index * Split virtual address into VPN (with index) and entry index
* for the given TLB way * for the given TLB way
*/ */
void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb, static void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v,
uint32_t *vpn, uint32_t wi, uint32_t *ei) bool dtlb, uint32_t *vpn,
uint32_t wi, uint32_t *ei)
{ {
bool varway56 = dtlb ? bool varway56 = dtlb ?
env->config->dtlb.varway56 : env->config->dtlb.varway56 :
@ -213,6 +214,14 @@ static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb,
} }
} }
static xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, bool dtlb,
unsigned wi, unsigned ei)
{
return dtlb ?
env->dtlb[wi] + ei :
env->itlb[wi] + ei;
}
static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env, static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env,
uint32_t v, bool dtlb, uint32_t *pwi) uint32_t v, bool dtlb, uint32_t *pwi)
{ {
@ -227,62 +236,7 @@ static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env,
return xtensa_tlb_get_entry(env, dtlb, wi, ei); return xtensa_tlb_get_entry(env, dtlb, wi, ei);
} }
uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) static void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
uint32_t wi;
const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
} else {
return v & REGION_PAGE_MASK;
}
}
uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
{
const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL);
return entry->paddr | entry->attr;
}
void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
uint32_t wi;
xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
if (entry->variable && entry->asid) {
tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr);
entry->asid = 0;
}
}
}
uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
uint32_t wi;
uint32_t ei;
uint8_t ring;
int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring);
switch (res) {
case 0:
if (ring >= xtensa_get_ring(env)) {
return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8);
}
break;
case INST_TLB_MULTI_HIT_CAUSE:
case LOAD_STORE_TLB_MULTI_HIT_CAUSE:
HELPER(exception_cause_vaddr)(env, env->pc, res, v);
break;
}
return 0;
} else {
return (v & REGION_PAGE_MASK) | 0x1;
}
}
void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
xtensa_tlb_entry *entry, bool dtlb, xtensa_tlb_entry *entry, bool dtlb,
unsigned wi, unsigned ei, uint32_t vpn, unsigned wi, unsigned ei, uint32_t vpn,
uint32_t pte) uint32_t pte)
@ -293,8 +247,9 @@ void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
entry->attr = pte & 0xf; entry->attr = pte & 0xf;
} }
void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, static void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) unsigned wi, unsigned ei,
uint32_t vpn, uint32_t pte)
{ {
XtensaCPU *cpu = xtensa_env_get_cpu(env); XtensaCPU *cpu = xtensa_env_get_cpu(env);
CPUState *cs = CPU(cpu); CPUState *cs = CPU(cpu);
@ -322,15 +277,6 @@ void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
} }
} }
void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb)
{
uint32_t vpn;
uint32_t wi;
uint32_t ei;
split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
}
hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{ {
XtensaCPU *cpu = XTENSA_CPU(cs); XtensaCPU *cpu = XTENSA_CPU(cs);
@ -462,7 +408,8 @@ static unsigned get_ring(const CPUXtensaState *env, uint8_t asid)
* \param pring: [out] access ring * \param pring: [out] access ring
* \return 0 if ok, exception cause code otherwise * \return 0 if ok, exception cause code otherwise
*/ */
int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb, static int xtensa_tlb_lookup(const CPUXtensaState *env,
uint32_t addr, bool dtlb,
uint32_t *pwi, uint32_t *pei, uint8_t *pring) uint32_t *pwi, uint32_t *pei, uint8_t *pring)
{ {
const xtensa_tlb *tlb = dtlb ? const xtensa_tlb *tlb = dtlb ?
@ -495,6 +442,70 @@ int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
(dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE); (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE);
} }
uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
uint32_t wi;
const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
} else {
return v & REGION_PAGE_MASK;
}
}
uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
{
const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL);
return entry->paddr | entry->attr;
}
void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
uint32_t wi;
xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
if (entry->variable && entry->asid) {
tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr);
entry->asid = 0;
}
}
}
uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
uint32_t wi;
uint32_t ei;
uint8_t ring;
int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring);
switch (res) {
case 0:
if (ring >= xtensa_get_ring(env)) {
return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8);
}
break;
case INST_TLB_MULTI_HIT_CAUSE:
case LOAD_STORE_TLB_MULTI_HIT_CAUSE:
HELPER(exception_cause_vaddr)(env, env->pc, res, v);
break;
}
return 0;
} else {
return (v & REGION_PAGE_MASK) | 0x1;
}
}
void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb)
{
uint32_t vpn;
uint32_t wi;
uint32_t ei;
split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
}
/*! /*!
* Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask. * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask.
* See ISA, 4.6.5.10 * See ISA, 4.6.5.10