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target/riscv: convert THead C906 to RISCVCPUDef

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Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2025-02-06 15:48:47 +01:00
parent 1016b0364f
commit 5f687d77ff
1 changed files with 28 additions and 33 deletions
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61
target/riscv/cpu.c
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@ -499,38 +499,6 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list)
#endif #endif
#if defined(TARGET_RISCV64) #if defined(TARGET_RISCV64)
static void rv64_thead_c906_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU);
env->priv_ver = PRIV_VERSION_1_11_0;
cpu->cfg.ext_zfa = true;
cpu->cfg.ext_zfh = true;
cpu->cfg.mmu = true;
cpu->cfg.ext_xtheadba = true;
cpu->cfg.ext_xtheadbb = true;
cpu->cfg.ext_xtheadbs = true;
cpu->cfg.ext_xtheadcmo = true;
cpu->cfg.ext_xtheadcondmov = true;
cpu->cfg.ext_xtheadfmemidx = true;
cpu->cfg.ext_xtheadmac = true;
cpu->cfg.ext_xtheadmemidx = true;
cpu->cfg.ext_xtheadmempair = true;
cpu->cfg.ext_xtheadsync = true;
cpu->cfg.mvendorid = THEAD_VENDOR_ID;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_SV39);
riscv_register_custom_csrs(cpu, th_csr_list);
#endif
/* inherited from parent obj via riscv_cpu_init() */
cpu->cfg.pmp = true;
}
static void rv64_veyron_v1_cpu_init(Object *obj) static void rv64_veyron_v1_cpu_init(Object *obj)
{ {
CPURISCVState *env = &RISCV_CPU(obj)->env; CPURISCVState *env = &RISCV_CPU(obj)->env;
@ -3217,7 +3185,34 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.misa_mxl_max = MXL_RV64, .misa_mxl_max = MXL_RV64,
), ),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c906_cpu_init), DEFINE_RISCV_CPU(TYPE_RISCV_CPU_THEAD_C906, TYPE_RISCV_VENDOR_CPU,
.misa_mxl_max = MXL_RV64,
.misa_ext = RVG | RVC | RVS | RVU,
.priv_spec = PRIV_VERSION_1_11_0,
.cfg.ext_zfa = true,
.cfg.ext_zfh = true,
.cfg.mmu = true,
.cfg.ext_xtheadba = true,
.cfg.ext_xtheadbb = true,
.cfg.ext_xtheadbs = true,
.cfg.ext_xtheadcmo = true,
.cfg.ext_xtheadcondmov = true,
.cfg.ext_xtheadfmemidx = true,
.cfg.ext_xtheadmac = true,
.cfg.ext_xtheadmemidx = true,
.cfg.ext_xtheadmempair = true,
.cfg.ext_xtheadsync = true,
.cfg.pmp = true,
.cfg.mvendorid = THEAD_VENDOR_ID,
.cfg.max_satp_mode = VM_1_10_SV39,
#ifndef CONFIG_USER_ONLY
.custom_csrs = th_csr_list,
#endif
),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_ascalon_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_ascalon_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,