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target/arm: Convert handle_fmov to decodetree
Remove disas_fp_int_conv and disas_data_proc_fp as these were the last insns decoded by those functions. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-35-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
a769f854e6
commit
5f4fe0e658
2 changed files with 86 additions and 160 deletions
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@ -1365,6 +1365,20 @@ FCVTAU_g . 0011110 .. 100101 000000 ..... ..... @icvt
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FJCVTZS 0 0011110 01 111110 000000 ..... ..... @rr
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FMOV_ws 0 0011110 00 100110 000000 ..... ..... @rr
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FMOV_sw 0 0011110 00 100111 000000 ..... ..... @rr
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FMOV_xd 1 0011110 01 100110 000000 ..... ..... @rr
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FMOV_dx 1 0011110 01 100111 000000 ..... ..... @rr
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# Move to/from upper half of 128-bit
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FMOV_xu 1 0011110 10 101110 000000 ..... ..... @rr
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FMOV_ux 1 0011110 10 101111 000000 ..... ..... @rr
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# Half-precision allows both sf=0 and sf=1 with identical results
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FMOV_xh - 0011110 11 100110 000000 ..... ..... @rr
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FMOV_hx - 0011110 11 100111 000000 ..... ..... @rr
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# Floating-point data processing (1 source)
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FMOV_s 00011110 .. 1 000000 10000 ..... ..... @rr_hsd
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@ -8734,175 +8734,87 @@ static bool trans_FJCVTZS(DisasContext *s, arg_FJCVTZS *a)
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return true;
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}
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static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
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static bool trans_FMOV_hx(DisasContext *s, arg_rr *a)
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{
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/* FMOV: gpr to or from float, double, or top half of quad fp reg,
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* without conversion.
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*/
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if (itof) {
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TCGv_i64 tcg_rn = cpu_reg(s, rn);
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TCGv_i64 tmp;
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switch (type) {
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case 0:
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/* 32 bit */
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tmp = tcg_temp_new_i64();
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tcg_gen_ext32u_i64(tmp, tcg_rn);
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write_fp_dreg(s, rd, tmp);
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break;
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case 1:
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/* 64 bit */
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write_fp_dreg(s, rd, tcg_rn);
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break;
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case 2:
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/* 64 bit to top half. */
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tcg_gen_st_i64(tcg_rn, tcg_env, fp_reg_hi_offset(s, rd));
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clear_vec_high(s, true, rd);
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break;
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case 3:
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/* 16 bit */
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tmp = tcg_temp_new_i64();
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tcg_gen_ext16u_i64(tmp, tcg_rn);
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write_fp_dreg(s, rd, tmp);
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break;
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default:
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g_assert_not_reached();
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}
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} else {
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TCGv_i64 tcg_rd = cpu_reg(s, rd);
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switch (type) {
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case 0:
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/* 32 bit */
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tcg_gen_ld32u_i64(tcg_rd, tcg_env, fp_reg_offset(s, rn, MO_32));
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break;
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case 1:
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/* 64 bit */
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tcg_gen_ld_i64(tcg_rd, tcg_env, fp_reg_offset(s, rn, MO_64));
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break;
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case 2:
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/* 64 bits from top half */
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tcg_gen_ld_i64(tcg_rd, tcg_env, fp_reg_hi_offset(s, rn));
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break;
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case 3:
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/* 16 bit */
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tcg_gen_ld16u_i64(tcg_rd, tcg_env, fp_reg_offset(s, rn, MO_16));
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break;
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default:
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g_assert_not_reached();
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}
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if (!dc_isar_feature(aa64_fp16, s)) {
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return false;
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}
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if (fp_access_check(s)) {
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TCGv_i64 tcg_rn = cpu_reg(s, a->rn);
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TCGv_i64 tmp = tcg_temp_new_i64();
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tcg_gen_ext16u_i64(tmp, tcg_rn);
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write_fp_dreg(s, a->rd, tmp);
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}
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return true;
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}
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/* Floating point <-> integer conversions
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* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
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* +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
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* | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
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* +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
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*/
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static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
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static bool trans_FMOV_sw(DisasContext *s, arg_rr *a)
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{
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int rd = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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int opcode = extract32(insn, 16, 3);
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int rmode = extract32(insn, 19, 2);
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int type = extract32(insn, 22, 2);
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bool sbit = extract32(insn, 29, 1);
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bool sf = extract32(insn, 31, 1);
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bool itof = false;
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if (sbit) {
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goto do_unallocated;
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}
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switch (opcode) {
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case 2: /* SCVTF */
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case 3: /* UCVTF */
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case 4: /* FCVTAS */
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case 5: /* FCVTAU */
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case 0: /* FCVT[NPMZ]S */
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case 1: /* FCVT[NPMZ]U */
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goto do_unallocated;
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default:
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switch (sf << 7 | type << 5 | rmode << 3 | opcode) {
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case 0b01100110: /* FMOV half <-> 32-bit int */
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case 0b01100111:
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case 0b11100110: /* FMOV half <-> 64-bit int */
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case 0b11100111:
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if (!dc_isar_feature(aa64_fp16, s)) {
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goto do_unallocated;
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}
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/* fallthru */
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case 0b00000110: /* FMOV 32-bit */
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case 0b00000111:
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case 0b10100110: /* FMOV 64-bit */
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case 0b10100111:
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case 0b11001110: /* FMOV top half of 128-bit */
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case 0b11001111:
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if (!fp_access_check(s)) {
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return;
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}
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itof = opcode & 1;
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handle_fmov(s, rd, rn, type, itof);
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break;
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case 0b00111110: /* FJCVTZS */
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default:
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do_unallocated:
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unallocated_encoding(s);
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return;
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}
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break;
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if (fp_access_check(s)) {
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TCGv_i64 tcg_rn = cpu_reg(s, a->rn);
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TCGv_i64 tmp = tcg_temp_new_i64();
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tcg_gen_ext32u_i64(tmp, tcg_rn);
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write_fp_dreg(s, a->rd, tmp);
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}
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return true;
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}
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/* FP-specific subcases of table C3-6 (SIMD and FP data processing)
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* 31 30 29 28 25 24 0
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* +---+---+---+---------+-----------------------------+
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* | | 0 | | 1 1 1 1 | |
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* +---+---+---+---------+-----------------------------+
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*/
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static void disas_data_proc_fp(DisasContext *s, uint32_t insn)
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static bool trans_FMOV_dx(DisasContext *s, arg_rr *a)
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{
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if (extract32(insn, 24, 1)) {
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unallocated_encoding(s); /* in decodetree */
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} else if (extract32(insn, 21, 1) == 0) {
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/* Floating point to fixed point conversions */
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unallocated_encoding(s); /* in decodetree */
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} else {
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switch (extract32(insn, 10, 2)) {
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case 1: /* Floating point conditional compare */
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case 2: /* Floating point data-processing (2 source) */
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case 3: /* Floating point conditional select */
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unallocated_encoding(s); /* in decodetree */
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break;
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case 0:
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switch (ctz32(extract32(insn, 12, 4))) {
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case 0: /* [15:12] == xxx1 */
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/* Floating point immediate */
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unallocated_encoding(s); /* in decodetree */
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break;
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case 1: /* [15:12] == xx10 */
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/* Floating point compare */
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unallocated_encoding(s); /* in decodetree */
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break;
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case 2: /* [15:12] == x100 */
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/* Floating point data-processing (1 source) */
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unallocated_encoding(s); /* in decodetree */
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break;
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case 3: /* [15:12] == 1000 */
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unallocated_encoding(s);
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break;
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default: /* [15:12] == 0000 */
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/* Floating point <-> integer conversions */
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disas_fp_int_conv(s, insn);
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break;
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}
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break;
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}
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if (fp_access_check(s)) {
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TCGv_i64 tcg_rn = cpu_reg(s, a->rn);
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write_fp_dreg(s, a->rd, tcg_rn);
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}
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return true;
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}
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static bool trans_FMOV_ux(DisasContext *s, arg_rr *a)
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{
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if (fp_access_check(s)) {
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TCGv_i64 tcg_rn = cpu_reg(s, a->rn);
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tcg_gen_st_i64(tcg_rn, tcg_env, fp_reg_hi_offset(s, a->rd));
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clear_vec_high(s, true, a->rd);
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}
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return true;
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}
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static bool trans_FMOV_xh(DisasContext *s, arg_rr *a)
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{
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if (!dc_isar_feature(aa64_fp16, s)) {
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return false;
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}
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if (fp_access_check(s)) {
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TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
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tcg_gen_ld16u_i64(tcg_rd, tcg_env, fp_reg_offset(s, a->rn, MO_16));
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}
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return true;
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}
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static bool trans_FMOV_ws(DisasContext *s, arg_rr *a)
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{
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if (fp_access_check(s)) {
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TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
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tcg_gen_ld32u_i64(tcg_rd, tcg_env, fp_reg_offset(s, a->rn, MO_32));
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}
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return true;
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}
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static bool trans_FMOV_xd(DisasContext *s, arg_rr *a)
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{
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if (fp_access_check(s)) {
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TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
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tcg_gen_ld_i64(tcg_rd, tcg_env, fp_reg_offset(s, a->rn, MO_64));
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}
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return true;
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}
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static bool trans_FMOV_xu(DisasContext *s, arg_rr *a)
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{
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if (fp_access_check(s)) {
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TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
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tcg_gen_ld_i64(tcg_rd, tcg_env, fp_reg_hi_offset(s, a->rn));
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}
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return true;
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}
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/* Common vector code for handling integer to FP conversion */
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@ -10821,7 +10733,7 @@ static void disas_data_proc_simd(DisasContext *s, uint32_t insn)
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static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn)
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{
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if (extract32(insn, 28, 1) == 1 && extract32(insn, 30, 1) == 0) {
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disas_data_proc_fp(s, insn);
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unallocated_encoding(s); /* in decodetree */
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} else {
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/* SIMD, including crypto */
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disas_data_proc_simd(s, insn);
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