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target-arm queue:
* hw/arm: Silence xlnx-ep108 deprecation warning during tests * hw/arm/aspeed: Unlock SCU when running kernel * arm: check regime, not current state, for ATS write PAR format * nvic: Fix ARMv7M MPU_RBAR reads * target/arm: Report GICv3 sysregs present in ID registers if needed -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJaExJdAAoJEDwlJe0UNgzeKCAP/0YzjL87it6HkbBzX9yP5Mpv UZk0HcNfrCGV69zy/4CiL33tqwwwSUZv16kVyNVtuqsJRDR3riy5C+YjqZBkvkCG iVAQ24i5NbSIvcOvNc4YBy2aA1FOU+qMbpdKZ1k8pkBwwLaNaY6OtbxwHYa9MqCZ iH/nylgRvOlNZKCmajRPudaagqEGrcj0xuszlhPM7HSYbYgYsnLabnaNJgSBLqxD MM4hCGFrJtNXDJoYu/FEZrKrWbuL9RHma31Vc2Fa1Lys9GO3sp+hhbZXDO7m/Q1L Id1/Q+EMAxuuSF7TyGAPBpKzHERTaOfYDqRY6CPcmBBxwwVx89E2KW49Tc8Gbijj i2tlWWrExUfMKnz51aoPaPrg97JIn3ql1UqsZ6RlqdZjT+pY3I3wt5o56Ys6PwCN 19J96AnMLKeglkSXztvsAGmo09uFRD4nuxueylUvrJoGCnPRbkvdJ1PDARw2XY8N gROwgw8eizxQ92d3yVzVl3v81jozwxX6X2ufNlLIiHRpg1LPTtQxWXxWJQobPia8 zZcm14QKF4r99UsfC/itkKi/D3ULUkH1r9eL8DH9EDyTd+E4rCuA+i8nlitDX7Tp 54UmWO62L9A6fidiYqNXTKJLLAosUpg0wGwWV4nN+7a2OaKembtbbs0Xyrb1uQOw ykdO9ZF2D5uwk7m20LrG =hxAO -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20171120' into staging target-arm queue: * hw/arm: Silence xlnx-ep108 deprecation warning during tests * hw/arm/aspeed: Unlock SCU when running kernel * arm: check regime, not current state, for ATS write PAR format * nvic: Fix ARMv7M MPU_RBAR reads * target/arm: Report GICv3 sysregs present in ID registers if needed # gpg: Signature made Mon 20 Nov 2017 17:35:25 GMT # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20171120: hw/arm: Silence xlnx-ep108 deprecation warning during tests hw/arm/aspeed: Unlock SCU when running kernel arm: check regime, not current state, for ATS write PAR format nvic: Fix ARMv7M MPU_RBAR reads target/arm: Report GICv3 sysregs present in ID registers if needed Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
5f49d73cb3
7 changed files with 64 additions and 10 deletions
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@ -29,6 +29,7 @@ typedef struct AspeedSCUState {
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uint32_t silicon_rev;
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uint32_t hw_strap1;
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uint32_t hw_strap2;
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uint32_t hw_prot_key;
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} AspeedSCUState;
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#define AST2400_A0_SILICON_REV 0x02000303U
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@ -38,6 +39,8 @@ typedef struct AspeedSCUState {
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extern bool is_supported_silicon_rev(uint32_t silicon_rev);
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#define ASPEED_SCU_PROT_KEY 0x1688A8A8
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/*
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* Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions
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* were added.
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