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target-alpha: Convert gen_ins_h/l to source/sink
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
9a734d64f9
commit
5e5863ecf1
1 changed files with 51 additions and 62 deletions
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@ -1235,75 +1235,64 @@ static void gen_ext_l(DisasContext *ctx, TCGv vc, TCGv va, int rb, bool islit,
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}
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}
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/* INSWH, INSLH, INSQH */
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/* INSWH, INSLH, INSQH */
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static void gen_ins_h(int ra, int rb, int rc, int islit,
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static void gen_ins_h(DisasContext *ctx, TCGv vc, TCGv va, int rb, bool islit,
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uint8_t lit, uint8_t byte_mask)
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uint8_t lit, uint8_t byte_mask)
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{
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{
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if (unlikely(rc == 31)) {
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TCGv tmp = tcg_temp_new();
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return;
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} else if (unlikely(ra == 31) || (islit && (lit & 7) == 0)) {
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tcg_gen_movi_i64(cpu_ir[rc], 0);
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} else {
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TCGv tmp = tcg_temp_new();
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/* The instruction description has us left-shift the byte mask
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/* The instruction description has us left-shift the byte mask and extract
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and extract bits <15:8> and apply that zap at the end. This
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bits <15:8> and apply that zap at the end. This is equivalent to simply
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is equivalent to simply performing the zap first and shifting
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performing the zap first and shifting afterward. */
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afterward. */
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gen_zapnoti(tmp, va, byte_mask);
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gen_zapnoti (tmp, cpu_ir[ra], byte_mask);
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if (islit) {
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if (islit) {
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/* Note that we have handled the lit==0 case above. */
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lit &= 7;
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tcg_gen_shri_i64 (cpu_ir[rc], tmp, 64 - (lit & 7) * 8);
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if (unlikely(lit == 0)) {
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tcg_gen_movi_i64(vc, 0);
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} else {
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} else {
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TCGv shift = tcg_temp_new();
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tcg_gen_shri_i64(vc, tmp, 64 - lit * 8);
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/* If (B & 7) == 0, we need to shift by 64 and leave a zero.
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Do this portably by splitting the shift into two parts:
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shift_count-1 and 1. Arrange for the -1 by using
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ones-complement instead of twos-complement in the negation:
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~((B & 7) * 8) & 63. */
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tcg_gen_andi_i64(shift, cpu_ir[rb], 7);
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tcg_gen_shli_i64(shift, shift, 3);
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tcg_gen_not_i64(shift, shift);
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tcg_gen_andi_i64(shift, shift, 0x3f);
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tcg_gen_shr_i64(cpu_ir[rc], tmp, shift);
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tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[rc], 1);
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tcg_temp_free(shift);
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}
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}
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tcg_temp_free(tmp);
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} else {
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TCGv shift = tcg_temp_new();
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/* If (B & 7) == 0, we need to shift by 64 and leave a zero. Do this
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portably by splitting the shift into two parts: shift_count-1 and 1.
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Arrange for the -1 by using ones-complement instead of
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twos-complement in the negation: ~(B * 8) & 63. */
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tcg_gen_shli_i64(shift, load_gpr(ctx, rb), 3);
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tcg_gen_not_i64(shift, shift);
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tcg_gen_andi_i64(shift, shift, 0x3f);
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tcg_gen_shr_i64(vc, tmp, shift);
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tcg_gen_shri_i64(vc, vc, 1);
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tcg_temp_free(shift);
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}
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}
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tcg_temp_free(tmp);
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}
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}
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/* INSBL, INSWL, INSLL, INSQL */
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/* INSBL, INSWL, INSLL, INSQL */
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static void gen_ins_l(int ra, int rb, int rc, int islit,
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static void gen_ins_l(DisasContext *ctx, TCGv vc, TCGv va, int rb, bool islit,
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uint8_t lit, uint8_t byte_mask)
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uint8_t lit, uint8_t byte_mask)
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{
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{
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if (unlikely(rc == 31)) {
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TCGv tmp = tcg_temp_new();
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return;
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} else if (unlikely(ra == 31)) {
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/* The instruction description has us left-shift the byte mask
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tcg_gen_movi_i64(cpu_ir[rc], 0);
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the same number of byte slots as the data and apply the zap
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at the end. This is equivalent to simply performing the zap
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first and shifting afterward. */
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gen_zapnoti(tmp, va, byte_mask);
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if (islit) {
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tcg_gen_shli_i64(vc, tmp, (lit & 7) * 8);
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} else {
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} else {
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TCGv tmp = tcg_temp_new();
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TCGv shift = tcg_temp_new();
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tcg_gen_andi_i64(shift, load_gpr(ctx, rb), 7);
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/* The instruction description has us left-shift the byte mask
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tcg_gen_shli_i64(shift, shift, 3);
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the same number of byte slots as the data and apply the zap
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tcg_gen_shl_i64(vc, tmp, shift);
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at the end. This is equivalent to simply performing the zap
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tcg_temp_free(shift);
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first and shifting afterward. */
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gen_zapnoti (tmp, cpu_ir[ra], byte_mask);
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if (islit) {
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tcg_gen_shli_i64(cpu_ir[rc], tmp, (lit & 7) * 8);
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} else {
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TCGv shift = tcg_temp_new();
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tcg_gen_andi_i64(shift, cpu_ir[rb], 7);
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tcg_gen_shli_i64(shift, shift, 3);
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tcg_gen_shl_i64(cpu_ir[rc], tmp, shift);
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tcg_temp_free(shift);
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}
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tcg_temp_free(tmp);
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}
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}
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tcg_temp_free(tmp);
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}
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}
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/* MSKWH, MSKLH, MSKQH */
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/* MSKWH, MSKLH, MSKQH */
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@ -2094,7 +2083,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
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break;
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break;
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case 0x0B:
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case 0x0B:
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/* INSBL */
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/* INSBL */
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gen_ins_l(ra, rb, rc, islit, lit, 0x01);
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gen_ins_l(ctx, vc, va, rb, islit, lit, 0x01);
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break;
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break;
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case 0x12:
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case 0x12:
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/* MSKWL */
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/* MSKWL */
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@ -2106,7 +2095,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
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break;
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break;
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case 0x1B:
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case 0x1B:
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/* INSWL */
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/* INSWL */
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gen_ins_l(ra, rb, rc, islit, lit, 0x03);
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gen_ins_l(ctx, vc, va, rb, islit, lit, 0x03);
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break;
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break;
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case 0x22:
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case 0x22:
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/* MSKLL */
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/* MSKLL */
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@ -2118,7 +2107,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
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break;
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break;
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case 0x2B:
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case 0x2B:
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/* INSLL */
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/* INSLL */
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gen_ins_l(ra, rb, rc, islit, lit, 0x0f);
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gen_ins_l(ctx, vc, va, rb, islit, lit, 0x0f);
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break;
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break;
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case 0x30:
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case 0x30:
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/* ZAP */
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/* ZAP */
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@ -2162,7 +2151,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
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break;
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break;
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case 0x3B:
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case 0x3B:
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/* INSQL */
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/* INSQL */
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gen_ins_l(ra, rb, rc, islit, lit, 0xff);
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gen_ins_l(ctx, vc, va, rb, islit, lit, 0xff);
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break;
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break;
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case 0x3C:
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case 0x3C:
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/* SRA */
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/* SRA */
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@ -2182,7 +2171,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
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break;
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break;
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case 0x57:
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case 0x57:
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/* INSWH */
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/* INSWH */
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gen_ins_h(ra, rb, rc, islit, lit, 0x03);
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gen_ins_h(ctx, vc, va, rb, islit, lit, 0x03);
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break;
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break;
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case 0x5A:
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case 0x5A:
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/* EXTWH */
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/* EXTWH */
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@ -2194,7 +2183,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
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break;
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break;
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case 0x67:
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case 0x67:
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/* INSLH */
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/* INSLH */
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gen_ins_h(ra, rb, rc, islit, lit, 0x0f);
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gen_ins_h(ctx, vc, va, rb, islit, lit, 0x0f);
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break;
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break;
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case 0x6A:
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case 0x6A:
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/* EXTLH */
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/* EXTLH */
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@ -2206,7 +2195,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
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break;
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break;
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case 0x77:
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case 0x77:
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/* INSQH */
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/* INSQH */
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gen_ins_h(ra, rb, rc, islit, lit, 0xff);
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gen_ins_h(ctx, vc, va, rb, islit, lit, 0xff);
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break;
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break;
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case 0x7A:
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case 0x7A:
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/* EXTQH */
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/* EXTQH */
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