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target/riscv: Add Smrnmi CSRs

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The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause',
'mnstatus' CSRs.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250106054336.1878291-3-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Tommy Wu 2025-01-06 13:43:32 +08:00 • committed by Alistair Francis
parent 36de64b74c
commit 5db557f82b
4 changed files with 105 additions and 0 deletions
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11
target/riscv/cpu_bits.h
View file

@ -353,6 +353,12 @@
#define CSR_PMPADDR14 0x3be
#define CSR_PMPADDR15 0x3bf
/* RNMI */
#define CSR_MNSCRATCH 0x740
#define CSR_MNEPC 0x741
#define CSR_MNCAUSE 0x742
#define CSR_MNSTATUS 0x744
/* Debug/Trace Registers (shared with Debug Mode) */
#define CSR_TSELECT 0x7a0
#define CSR_TDATA1 0x7a1
@ -604,6 +610,11 @@ typedef enum {
#define SATP64_ASID 0x0FFFF00000000000ULL
#define SATP64_PPN 0x00000FFFFFFFFFFFULL
/* RNMI mnstatus CSR mask */
#define MNSTATUS_NMIE 0x00000008
#define MNSTATUS_MNPV 0x00000080
#define MNSTATUS_MNPP 0x00001800
/* VM modes (satp.mode) privileged ISA 1.10 */
#define VM_1_10_MBARE 0
#define VM_1_10_SV32 1