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ppc/pnv: POWER9 XSCOM quad support

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The POWER9 processor does not support per-core frequency control. The
cores are arranged in groups of four, along with their respective L2
and L3 caches, into a structure known as a Quad. The frequency must be
managed at the Quad level.

Provide a basic Quad model to fake the settings done by the firmware
on the Non-Cacheable Unit (NCU). Each core pair (EX) needs a special
BAR setting for the TIMA area of XIVE because it resides on the same
address on all chips.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190307223548.20516-12-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater 2019-03-07 23:35:44 +01:00 • committed by David Gibson
parent 90ef386c74
commit 5dad902ce0
5 changed files with 146 additions and 5 deletions
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10
include/hw/ppc/pnv_core.h
View file

@ -58,4 +58,14 @@ static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu)
return (PnvCPUState *)cpu->machine_data;
}
#define TYPE_PNV_QUAD "powernv-cpu-quad"
#define PNV_QUAD(obj) \
OBJECT_CHECK(PnvQuad, (obj), TYPE_PNV_QUAD)
typedef struct PnvQuad {
DeviceState parent_obj;
uint32_t id;
MemoryRegion xscom_regs;
} PnvQuad;
#endif /* _PPC_PNV_CORE_H */