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ppc/pnv: POWER9 XSCOM quad support
The POWER9 processor does not support per-core frequency control. The cores are arranged in groups of four, along with their respective L2 and L3 caches, into a structure known as a Quad. The frequency must be managed at the Quad level. Provide a basic Quad model to fake the settings done by the firmware on the Non-Cacheable Unit (NCU). Each core pair (EX) needs a special BAR setting for the TIMA area of XIVE because it resides on the same address on all chips. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-12-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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5 changed files with 146 additions and 5 deletions
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@ -26,6 +26,7 @@
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#include "hw/ppc/pnv_psi.h"
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#include "hw/ppc/pnv_occ.h"
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#include "hw/ppc/pnv_xive.h"
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#include "hw/ppc/pnv_core.h"
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#define TYPE_PNV_CHIP "pnv-chip"
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#define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
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@ -89,6 +90,9 @@ typedef struct Pnv9Chip {
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Pnv9Psi psi;
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PnvLpcController lpc;
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PnvOCC occ;
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uint32_t nr_quads;
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PnvQuad *quads;
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} Pnv9Chip;
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typedef struct PnvChipClass {
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@ -58,4 +58,14 @@ static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu)
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return (PnvCPUState *)cpu->machine_data;
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}
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#define TYPE_PNV_QUAD "powernv-cpu-quad"
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#define PNV_QUAD(obj) \
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OBJECT_CHECK(PnvQuad, (obj), TYPE_PNV_QUAD)
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typedef struct PnvQuad {
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DeviceState parent_obj;
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uint32_t id;
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MemoryRegion xscom_regs;
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} PnvQuad;
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#endif /* _PPC_PNV_CORE_H */
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@ -60,10 +60,6 @@ typedef struct PnvXScomInterfaceClass {
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(PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24))
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#define PNV_XSCOM_EX_SIZE 0x100000
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#define PNV_XSCOM_P9_EC_BASE(core) \
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((uint64_t)(((core) & 0x1F) + 0x20) << 24)
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#define PNV_XSCOM_P9_EC_SIZE 0x100000
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#define PNV_XSCOM_LPC_BASE 0xb0020
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#define PNV_XSCOM_LPC_SIZE 0x4
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@ -73,6 +69,14 @@ typedef struct PnvXScomInterfaceClass {
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#define PNV_XSCOM_OCC_BASE 0x0066000
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#define PNV_XSCOM_OCC_SIZE 0x6000
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#define PNV9_XSCOM_EC_BASE(core) \
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((uint64_t)(((core) & 0x1F) + 0x20) << 24)
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#define PNV9_XSCOM_EC_SIZE 0x100000
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#define PNV9_XSCOM_EQ_BASE(core) \
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((uint64_t)(((core) & 0x1C) + 0x40) << 22)
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#define PNV9_XSCOM_EQ_SIZE 0x100000
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#define PNV9_XSCOM_OCC_BASE PNV_XSCOM_OCC_BASE
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#define PNV9_XSCOM_OCC_SIZE 0x8000
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