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test/qtest/hace: Support 64-bit source and digest addresses for AST2700

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Added "HACE_HASH_SRC_HI" and "HACE_HASH_DIGEST_HI", "HACE_HASH_KEY_BUFF_HI"
registers to store upper 32 bits.
Updated "write_regs" to handle 64-bit source and digest addresses.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Acked-by: Fabiano Rosas <farosas@suse.de>
Link: https://lore.kernel.org/qemu-devel/20250515081008.583578-26-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-05-15 16:09:57 +08:00 • committed by Cédric Le Goater
parent dcdbbd45a8
commit 5ced818e42
2 changed files with 5 additions and 0 deletions
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2
tests/qtest/aspeed-hace-utils.c
View file

@ -157,7 +157,9 @@ static void write_regs(QTestState *s, uint32_t base, uint64_t src,
uint32_t length, uint64_t out, uint32_t method)
{
qtest_writel(s, base + HACE_HASH_SRC, extract64(src, 0, 32));
qtest_writel(s, base + HACE_HASH_SRC_HI, extract64(src, 32, 32));
qtest_writel(s, base + HACE_HASH_DIGEST, extract64(out, 0, 32));
qtest_writel(s, base + HACE_HASH_DIGEST_HI, extract64(out, 32, 32));
qtest_writel(s, base + HACE_HASH_DATA_LEN, length);
qtest_writel(s, base + HACE_HASH_CMD, HACE_SHA_BE_EN | method);
}

3
tests/qtest/aspeed-hace-utils.h
View file

@ -36,6 +36,9 @@
#define HACE_HASH_KEY_BUFF 0x28
#define HACE_HASH_DATA_LEN 0x2c
#define HACE_HASH_CMD 0x30
#define HACE_HASH_SRC_HI 0x90
#define HACE_HASH_DIGEST_HI 0x94
#define HACE_HASH_KEY_BUFF_HI 0x98
/* Scatter-Gather Hash */
#define SG_LIST_LEN_LAST BIT(31)