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target-arm queue:

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* target/arm: refactoring for compile-twice changes
  * MAINTAINERS: Add an entry for the Bananapi machine
  * arm/omap: remove hard coded tabs
  * rust: pl011: Cut down amount of text quoted from PL011 TRM
  * target/arm: refactor Arm CPU class hierarchy
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Merge tag 'pull-target-arm-20250515' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * target/arm: refactoring for compile-twice changes
 * MAINTAINERS: Add an entry for the Bananapi machine
 * arm/omap: remove hard coded tabs
 * rust: pl011: Cut down amount of text quoted from PL011 TRM
 * target/arm: refactor Arm CPU class hierarchy

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# gpg: Signature made Thu 15 May 2025 06:23:01 EDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20250515' of https://git.linaro.org/people/pmaydell/qemu-arm: (58 commits)
  target/arm/tcg/vfp_helper: compile file twice (system, user)
  target/arm/tcg/arith_helper: compile file once
  target/arm/tcg/tlb-insns: compile file once (system)
  target/arm/helper: restrict define_tlb_insn_regs to system target
  target/arm/tcg/tlb_helper: compile file twice (system, user)
  target/arm/tcg/neon_helper: compile file twice (system, user)
  target/arm/tcg/iwmmxt_helper: compile file twice (system, user)
  target/arm/tcg/hflags: compile file twice (system, user)
  target/arm/tcg/crypto_helper: compile file once
  target/arm/tcg/vec_internal: use forward declaration for CPUARMState
  target/arm/machine: compile file once (system)
  target/arm/kvm-stub: add missing stubs
  target/arm/machine: move cpu_post_load kvm bits to kvm_arm_cpu_post_load function
  target/arm/machine: remove TARGET_AARCH64 from migration state
  target/arm/machine: reduce migration include to avoid target specific definitions
  target/arm/kvm-stub: compile file once (system)
  target/arm/meson: accelerator files are not needed in user mode
  target/arm/ptw: compile file once (system)
  target/arm/ptw: replace TARGET_AARCH64 by CONFIG_ATOMIC64 from arm_casq_ptw
  target/arm/ptw: replace target_ulong with int64_t
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2025-05-15 13:42:20 -04:00
commit 5cb8b0988b
53 changed files with 3033 additions and 3100 deletions
Download patch file Download diff file Expand all files Collapse all files

10
MAINTAINERS
View file

@ -732,6 +732,16 @@ F: include/hw/timer/armv7m_systick.h
F: include/hw/misc/armv7m_ras.h F: include/hw/misc/armv7m_ras.h
F: tests/qtest/test-arm-mptimer.c F: tests/qtest/test-arm-mptimer.c
Bananapi M2U
M: Peter Maydell <peter.maydell@linaro.org>
L: qemu-arm@nongnu.org
S: Odd Fixes
F: docs/system/arm/bananapi_m2u.rst
F: hw/*/allwinner-r40*.c
F: hw/arm/bananapi_m2u.c
F: include/hw/*/allwinner-r40*.h
F: tests/functional/test_arm_bpim2u.py
B-L475E-IOT01A IoT Node B-L475E-IOT01A IoT Node
M: Samuel Tardieu <sam@rfc1149.net> M: Samuel Tardieu <sam@rfc1149.net>
L: qemu-arm@nongnu.org L: qemu-arm@nongnu.org

1016
hw/arm/omap1.c
View file

File diff suppressed because it is too large Load diff

2
hw/arm/omap_sx1.c
View file

@ -1,7 +1,7 @@
/* omap_sx1.c Support for the Siemens SX1 smartphone emulation. /* omap_sx1.c Support for the Siemens SX1 smartphone emulation.
* *
* Copyright (C) 2008 * Copyright (C) 2008
* Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Copyright (C) 2007 Vladimir Ananiev <vovan888@gmail.com> * Copyright (C) 2007 Vladimir Ananiev <vovan888@gmail.com>
* *
* based on PalmOne's (TM) PDAs support (palm.c) * based on PalmOne's (TM) PDAs support (palm.c)

3
hw/core/cpu-common.c
View file

@ -234,6 +234,8 @@ bool cpu_exec_realizefn(CPUState *cpu, Error **errp)
return false; return false;
} }
gdb_init_cpu(cpu);
/* Wait until cpu initialization complete before exposing cpu. */ /* Wait until cpu initialization complete before exposing cpu. */
cpu_list_add(cpu); cpu_list_add(cpu);
@ -304,7 +306,6 @@ static void cpu_common_initfn(Object *obj)
/* cache the cpu class for the hotpath */ /* cache the cpu class for the hotpath */
cpu->cc = CPU_GET_CLASS(cpu); cpu->cc = CPU_GET_CLASS(cpu);
gdb_init_cpu(cpu);
cpu->cpu_index = UNASSIGNED_CPU_INDEX; cpu->cpu_index = UNASSIGNED_CPU_INDEX;
cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX; cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX;
cpu->as = NULL; cpu->as = NULL;

334
hw/dma/omap_dma.c
View file

@ -131,9 +131,9 @@ struct omap_dma_s {
#define LAST_FRAME_INTR (1 << 4) #define LAST_FRAME_INTR (1 << 4)
#define END_BLOCK_INTR (1 << 5) #define END_BLOCK_INTR (1 << 5)
#define SYNC (1 << 6) #define SYNC (1 << 6)
#define END_PKT_INTR (1 << 7) #define END_PKT_INTR (1 << 7)
#define TRANS_ERR_INTR (1 << 8) #define TRANS_ERR_INTR (1 << 8)
#define MISALIGN_INTR (1 << 11) #define MISALIGN_INTR (1 << 11)
static inline void omap_dma_interrupts_update(struct omap_dma_s *s) static inline void omap_dma_interrupts_update(struct omap_dma_s *s)
{ {
@ -526,12 +526,12 @@ static void omap_dma_transfer_setup(struct soc_dma_ch_s *dma)
/* Check all the conditions that terminate the transfer starting /* Check all the conditions that terminate the transfer starting
* with those that can occur the soonest. */ * with those that can occur the soonest. */
#define INTR_CHECK(cond, id, nelements) \ #define INTR_CHECK(cond, id, nelements) \
if (cond) { \ if (cond) { \
elements[id] = nelements; \ elements[id] = nelements; \
if (elements[id] < min_elems) \ if (elements[id] < min_elems) \
min_elems = elements[id]; \ min_elems = elements[id]; \
} else \ } else \
elements[id] = INT_MAX; elements[id] = INT_MAX;
/* Elements */ /* Elements */
@ -740,7 +740,7 @@ static int omap_dma_ch_reg_read(struct omap_dma_s *s,
struct omap_dma_channel_s *ch, int reg, uint16_t *value) struct omap_dma_channel_s *ch, int reg, uint16_t *value)
{ {
switch (reg) { switch (reg) {
case 0x00: /* SYS_DMA_CSDP_CH0 */ case 0x00: /* SYS_DMA_CSDP_CH0 */
*value = (ch->burst[1] << 14) | *value = (ch->burst[1] << 14) |
(ch->pack[1] << 13) | (ch->pack[1] << 13) |
(ch->port[1] << 9) | (ch->port[1] << 9) |
@ -750,9 +750,9 @@ static int omap_dma_ch_reg_read(struct omap_dma_s *s,
(ch->data_type >> 1); (ch->data_type >> 1);
break; break;
case 0x02: /* SYS_DMA_CCR_CH0 */ case 0x02: /* SYS_DMA_CCR_CH0 */
if (s->model <= omap_dma_3_1) if (s->model <= omap_dma_3_1)
*value = 0 << 10; /* FIFO_FLUSH reads as 0 */ *value = 0 << 10; /* FIFO_FLUSH reads as 0 */
else else
*value = ch->omap_3_1_compatible_disable << 10; *value = ch->omap_3_1_compatible_disable << 10;
*value |= (ch->mode[1] << 14) | *value |= (ch->mode[1] << 14) |
@ -765,11 +765,11 @@ static int omap_dma_ch_reg_read(struct omap_dma_s *s,
(ch->fs << 5) | ch->sync; (ch->fs << 5) | ch->sync;
break; break;
case 0x04: /* SYS_DMA_CICR_CH0 */ case 0x04: /* SYS_DMA_CICR_CH0 */
*value = ch->interrupts; *value = ch->interrupts;
break; break;
case 0x06: /* SYS_DMA_CSR_CH0 */ case 0x06: /* SYS_DMA_CSR_CH0 */
*value = ch->status; *value = ch->status;
ch->status &= SYNC; ch->status &= SYNC;
if (!ch->omap_3_1_compatible_disable && ch->sibling) { if (!ch->omap_3_1_compatible_disable && ch->sibling) {
@ -779,77 +779,77 @@ static int omap_dma_ch_reg_read(struct omap_dma_s *s,
qemu_irq_lower(ch->irq); qemu_irq_lower(ch->irq);
break; break;
case 0x08: /* SYS_DMA_CSSA_L_CH0 */ case 0x08: /* SYS_DMA_CSSA_L_CH0 */
*value = ch->addr[0] & 0x0000ffff; *value = ch->addr[0] & 0x0000ffff;
break; break;
case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
*value = ch->addr[0] >> 16; *value = ch->addr[0] >> 16;
break; break;
case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
*value = ch->addr[1] & 0x0000ffff; *value = ch->addr[1] & 0x0000ffff;
break; break;
case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
*value = ch->addr[1] >> 16; *value = ch->addr[1] >> 16;
break; break;
case 0x10: /* SYS_DMA_CEN_CH0 */ case 0x10: /* SYS_DMA_CEN_CH0 */
*value = ch->elements; *value = ch->elements;
break; break;
case 0x12: /* SYS_DMA_CFN_CH0 */ case 0x12: /* SYS_DMA_CFN_CH0 */
*value = ch->frames; *value = ch->frames;
break; break;
case 0x14: /* SYS_DMA_CFI_CH0 */ case 0x14: /* SYS_DMA_CFI_CH0 */
*value = ch->frame_index[0]; *value = ch->frame_index[0];
break; break;
case 0x16: /* SYS_DMA_CEI_CH0 */ case 0x16: /* SYS_DMA_CEI_CH0 */
*value = ch->element_index[0]; *value = ch->element_index[0];
break; break;
case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
if (ch->omap_3_1_compatible_disable) if (ch->omap_3_1_compatible_disable)
*value = ch->active_set.src & 0xffff; /* CSAC */ *value = ch->active_set.src & 0xffff; /* CSAC */
else else
*value = ch->cpc; *value = ch->cpc;
break; break;
case 0x1a: /* DMA_CDAC */ case 0x1a: /* DMA_CDAC */
*value = ch->active_set.dest & 0xffff; /* CDAC */ *value = ch->active_set.dest & 0xffff; /* CDAC */
break; break;
case 0x1c: /* DMA_CDEI */ case 0x1c: /* DMA_CDEI */
*value = ch->element_index[1]; *value = ch->element_index[1];
break; break;
case 0x1e: /* DMA_CDFI */ case 0x1e: /* DMA_CDFI */
*value = ch->frame_index[1]; *value = ch->frame_index[1];
break; break;
case 0x20: /* DMA_COLOR_L */ case 0x20: /* DMA_COLOR_L */
*value = ch->color & 0xffff; *value = ch->color & 0xffff;
break; break;
case 0x22: /* DMA_COLOR_U */ case 0x22: /* DMA_COLOR_U */
*value = ch->color >> 16; *value = ch->color >> 16;
break; break;
case 0x24: /* DMA_CCR2 */ case 0x24: /* DMA_CCR2 */
*value = (ch->bs << 2) | *value = (ch->bs << 2) |
(ch->transparent_copy << 1) | (ch->transparent_copy << 1) |
ch->constant_fill; ch->constant_fill;
break; break;
case 0x28: /* DMA_CLNK_CTRL */ case 0x28: /* DMA_CLNK_CTRL */
*value = (ch->link_enabled << 15) | *value = (ch->link_enabled << 15) |
(ch->link_next_ch & 0xf); (ch->link_next_ch & 0xf);
break; break;
case 0x2a: /* DMA_LCH_CTRL */ case 0x2a: /* DMA_LCH_CTRL */
*value = (ch->interleave_disabled << 15) | *value = (ch->interleave_disabled << 15) |
ch->type; ch->type;
break; break;
@ -864,7 +864,7 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,
struct omap_dma_channel_s *ch, int reg, uint16_t value) struct omap_dma_channel_s *ch, int reg, uint16_t value)
{ {
switch (reg) { switch (reg) {
case 0x00: /* SYS_DMA_CSDP_CH0 */ case 0x00: /* SYS_DMA_CSDP_CH0 */
ch->burst[1] = (value & 0xc000) >> 14; ch->burst[1] = (value & 0xc000) >> 14;
ch->pack[1] = (value & 0x2000) >> 13; ch->pack[1] = (value & 0x2000) >> 13;
ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9); ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9);
@ -887,7 +887,7 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,
} }
break; break;
case 0x02: /* SYS_DMA_CCR_CH0 */ case 0x02: /* SYS_DMA_CCR_CH0 */
ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
ch->end_prog = (value & 0x0800) >> 11; ch->end_prog = (value & 0x0800) >> 11;
@ -909,88 +909,88 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,
break; break;
case 0x04: /* SYS_DMA_CICR_CH0 */ case 0x04: /* SYS_DMA_CICR_CH0 */
ch->interrupts = value & 0x3f; ch->interrupts = value & 0x3f;
break; break;
case 0x06: /* SYS_DMA_CSR_CH0 */ case 0x06: /* SYS_DMA_CSR_CH0 */
OMAP_RO_REG((hwaddr) reg); OMAP_RO_REG((hwaddr) reg);
break; break;
case 0x08: /* SYS_DMA_CSSA_L_CH0 */ case 0x08: /* SYS_DMA_CSSA_L_CH0 */
ch->addr[0] &= 0xffff0000; ch->addr[0] &= 0xffff0000;
ch->addr[0] |= value; ch->addr[0] |= value;
break; break;
case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
ch->addr[0] &= 0x0000ffff; ch->addr[0] &= 0x0000ffff;
ch->addr[0] |= (uint32_t) value << 16; ch->addr[0] |= (uint32_t) value << 16;
break; break;
case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
ch->addr[1] &= 0xffff0000; ch->addr[1] &= 0xffff0000;
ch->addr[1] |= value; ch->addr[1] |= value;
break; break;
case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
ch->addr[1] &= 0x0000ffff; ch->addr[1] &= 0x0000ffff;
ch->addr[1] |= (uint32_t) value << 16; ch->addr[1] |= (uint32_t) value << 16;
break; break;
case 0x10: /* SYS_DMA_CEN_CH0 */ case 0x10: /* SYS_DMA_CEN_CH0 */
ch->elements = value; ch->elements = value;
break; break;
case 0x12: /* SYS_DMA_CFN_CH0 */ case 0x12: /* SYS_DMA_CFN_CH0 */
ch->frames = value; ch->frames = value;
break; break;
case 0x14: /* SYS_DMA_CFI_CH0 */ case 0x14: /* SYS_DMA_CFI_CH0 */
ch->frame_index[0] = (int16_t) value; ch->frame_index[0] = (int16_t) value;
break; break;
case 0x16: /* SYS_DMA_CEI_CH0 */ case 0x16: /* SYS_DMA_CEI_CH0 */
ch->element_index[0] = (int16_t) value; ch->element_index[0] = (int16_t) value;
break; break;
case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
OMAP_RO_REG((hwaddr) reg); OMAP_RO_REG((hwaddr) reg);
break; break;
case 0x1c: /* DMA_CDEI */ case 0x1c: /* DMA_CDEI */
ch->element_index[1] = (int16_t) value; ch->element_index[1] = (int16_t) value;
break; break;
case 0x1e: /* DMA_CDFI */ case 0x1e: /* DMA_CDFI */
ch->frame_index[1] = (int16_t) value; ch->frame_index[1] = (int16_t) value;
break; break;
case 0x20: /* DMA_COLOR_L */ case 0x20: /* DMA_COLOR_L */
ch->color &= 0xffff0000; ch->color &= 0xffff0000;
ch->color |= value; ch->color |= value;
break; break;
case 0x22: /* DMA_COLOR_U */ case 0x22: /* DMA_COLOR_U */
ch->color &= 0xffff; ch->color &= 0xffff;
ch->color |= (uint32_t)value << 16; ch->color |= (uint32_t)value << 16;
break; break;
case 0x24: /* DMA_CCR2 */ case 0x24: /* DMA_CCR2 */
ch->bs = (value >> 2) & 0x1; ch->bs = (value >> 2) & 0x1;
ch->transparent_copy = (value >> 1) & 0x1; ch->transparent_copy = (value >> 1) & 0x1;
ch->constant_fill = value & 0x1; ch->constant_fill = value & 0x1;
break; break;
case 0x28: /* DMA_CLNK_CTRL */ case 0x28: /* DMA_CLNK_CTRL */
ch->link_enabled = (value >> 15) & 0x1; ch->link_enabled = (value >> 15) & 0x1;
if (value & (1 << 14)) { /* Stop_Lnk */ if (value & (1 << 14)) { /* Stop_Lnk */
ch->link_enabled = 0; ch->link_enabled = 0;
omap_dma_disable_channel(s, ch); omap_dma_disable_channel(s, ch);
} }
ch->link_next_ch = value & 0x1f; ch->link_next_ch = value & 0x1f;
break; break;
case 0x2a: /* DMA_LCH_CTRL */ case 0x2a: /* DMA_LCH_CTRL */
ch->interleave_disabled = (value >> 15) & 0x1; ch->interleave_disabled = (value >> 15) & 0x1;
ch->type = value & 0xf; ch->type = value & 0xf;
break; break;
@ -1005,7 +1005,7 @@ static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
uint16_t value) uint16_t value)
{ {
switch (offset) { switch (offset) {
case 0xbc0: /* DMA_LCD_CSDP */ case 0xbc0: /* DMA_LCD_CSDP */
s->brust_f2 = (value >> 14) & 0x3; s->brust_f2 = (value >> 14) & 0x3;
s->pack_f2 = (value >> 13) & 0x1; s->pack_f2 = (value >> 13) & 0x1;
s->data_type_f2 = (1 << ((value >> 11) & 0x3)); s->data_type_f2 = (1 << ((value >> 11) & 0x3));
@ -1014,7 +1014,7 @@ static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
s->data_type_f1 = (1 << ((value >> 0) & 0x3)); s->data_type_f1 = (1 << ((value >> 0) & 0x3));
break; break;
case 0xbc2: /* DMA_LCD_CCR */ case 0xbc2: /* DMA_LCD_CCR */
s->mode_f2 = (value >> 14) & 0x3; s->mode_f2 = (value >> 14) & 0x3;
s->mode_f1 = (value >> 12) & 0x3; s->mode_f1 = (value >> 12) & 0x3;
s->end_prog = (value >> 11) & 0x1; s->end_prog = (value >> 11) & 0x1;
@ -1026,7 +1026,7 @@ static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
s->bs = (value >> 4) & 0x1; s->bs = (value >> 4) & 0x1;
break; break;
case 0xbc4: /* DMA_LCD_CTRL */ case 0xbc4: /* DMA_LCD_CTRL */
s->dst = (value >> 8) & 0x1; s->dst = (value >> 8) & 0x1;
s->src = ((value >> 6) & 0x3) << 1; s->src = ((value >> 6) & 0x3) << 1;
s->condition = 0; s->condition = 0;
@ -1035,91 +1035,91 @@ static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
s->dual = value & 1; s->dual = value & 1;
break; break;
case 0xbc8: /* TOP_B1_L */ case 0xbc8: /* TOP_B1_L */
s->src_f1_top &= 0xffff0000; s->src_f1_top &= 0xffff0000;
s->src_f1_top |= 0x0000ffff & value; s->src_f1_top |= 0x0000ffff & value;
break; break;
case 0xbca: /* TOP_B1_U */ case 0xbca: /* TOP_B1_U */
s->src_f1_top &= 0x0000ffff; s->src_f1_top &= 0x0000ffff;
s->src_f1_top |= (uint32_t)value << 16; s->src_f1_top |= (uint32_t)value << 16;
break; break;
case 0xbcc: /* BOT_B1_L */ case 0xbcc: /* BOT_B1_L */
s->src_f1_bottom &= 0xffff0000; s->src_f1_bottom &= 0xffff0000;
s->src_f1_bottom |= 0x0000ffff & value; s->src_f1_bottom |= 0x0000ffff & value;
break; break;
case 0xbce: /* BOT_B1_U */ case 0xbce: /* BOT_B1_U */
s->src_f1_bottom &= 0x0000ffff; s->src_f1_bottom &= 0x0000ffff;
s->src_f1_bottom |= (uint32_t) value << 16; s->src_f1_bottom |= (uint32_t) value << 16;
break; break;
case 0xbd0: /* TOP_B2_L */ case 0xbd0: /* TOP_B2_L */
s->src_f2_top &= 0xffff0000; s->src_f2_top &= 0xffff0000;
s->src_f2_top |= 0x0000ffff & value; s->src_f2_top |= 0x0000ffff & value;
break; break;
case 0xbd2: /* TOP_B2_U */ case 0xbd2: /* TOP_B2_U */
s->src_f2_top &= 0x0000ffff; s->src_f2_top &= 0x0000ffff;
s->src_f2_top |= (uint32_t) value << 16; s->src_f2_top |= (uint32_t) value << 16;
break; break;
case 0xbd4: /* BOT_B2_L */ case 0xbd4: /* BOT_B2_L */
s->src_f2_bottom &= 0xffff0000; s->src_f2_bottom &= 0xffff0000;
s->src_f2_bottom |= 0x0000ffff & value; s->src_f2_bottom |= 0x0000ffff & value;
break; break;
case 0xbd6: /* BOT_B2_U */ case 0xbd6: /* BOT_B2_U */
s->src_f2_bottom &= 0x0000ffff; s->src_f2_bottom &= 0x0000ffff;
s->src_f2_bottom |= (uint32_t) value << 16; s->src_f2_bottom |= (uint32_t) value << 16;
break; break;
case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
s->element_index_f1 = value; s->element_index_f1 = value;
break; break;
case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
s->frame_index_f1 &= 0xffff0000; s->frame_index_f1 &= 0xffff0000;
s->frame_index_f1 |= 0x0000ffff & value; s->frame_index_f1 |= 0x0000ffff & value;
break; break;
case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
s->frame_index_f1 &= 0x0000ffff; s->frame_index_f1 &= 0x0000ffff;
s->frame_index_f1 |= (uint32_t) value << 16; s->frame_index_f1 |= (uint32_t) value << 16;
break; break;
case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
s->element_index_f2 = value; s->element_index_f2 = value;
break; break;
case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
s->frame_index_f2 &= 0xffff0000; s->frame_index_f2 &= 0xffff0000;
s->frame_index_f2 |= 0x0000ffff & value; s->frame_index_f2 |= 0x0000ffff & value;
break; break;
case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
s->frame_index_f2 &= 0x0000ffff; s->frame_index_f2 &= 0x0000ffff;
s->frame_index_f2 |= (uint32_t) value << 16; s->frame_index_f2 |= (uint32_t) value << 16;
break; break;
case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
s->elements_f1 = value; s->elements_f1 = value;
break; break;
case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
s->frames_f1 = value; s->frames_f1 = value;
break; break;
case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
s->elements_f2 = value; s->elements_f2 = value;
break; break;
case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
s->frames_f2 = value; s->frames_f2 = value;
break; break;
case 0xbea: /* DMA_LCD_LCH_CTRL */ case 0xbea: /* DMA_LCD_LCH_CTRL */
s->lch_type = value & 0xf; s->lch_type = value & 0xf;
break; break;
@ -1133,7 +1133,7 @@ static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
uint16_t *ret) uint16_t *ret)
{ {
switch (offset) { switch (offset) {
case 0xbc0: /* DMA_LCD_CSDP */ case 0xbc0: /* DMA_LCD_CSDP */
*ret = (s->brust_f2 << 14) | *ret = (s->brust_f2 << 14) |
(s->pack_f2 << 13) | (s->pack_f2 << 13) |
((s->data_type_f2 >> 1) << 11) | ((s->data_type_f2 >> 1) << 11) |
@ -1142,7 +1142,7 @@ static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
((s->data_type_f1 >> 1) << 0); ((s->data_type_f1 >> 1) << 0);
break; break;
case 0xbc2: /* DMA_LCD_CCR */ case 0xbc2: /* DMA_LCD_CCR */
*ret = (s->mode_f2 << 14) | *ret = (s->mode_f2 << 14) |
(s->mode_f1 << 12) | (s->mode_f1 << 12) |
(s->end_prog << 11) | (s->end_prog << 11) |
@ -1154,7 +1154,7 @@ static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
(s->bs << 4); (s->bs << 4);
break; break;
case 0xbc4: /* DMA_LCD_CTRL */ case 0xbc4: /* DMA_LCD_CTRL */
qemu_irq_lower(s->irq); qemu_irq_lower(s->irq);
*ret = (s->dst << 8) | *ret = (s->dst << 8) |
((s->src & 0x6) << 5) | ((s->src & 0x6) << 5) |
@ -1163,79 +1163,79 @@ static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
s->dual; s->dual;
break; break;
case 0xbc8: /* TOP_B1_L */ case 0xbc8: /* TOP_B1_L */
*ret = s->src_f1_top & 0xffff; *ret = s->src_f1_top & 0xffff;
break; break;
case 0xbca: /* TOP_B1_U */ case 0xbca: /* TOP_B1_U */
*ret = s->src_f1_top >> 16; *ret = s->src_f1_top >> 16;
break; break;
case 0xbcc: /* BOT_B1_L */ case 0xbcc: /* BOT_B1_L */
*ret = s->src_f1_bottom & 0xffff; *ret = s->src_f1_bottom & 0xffff;
break; break;
case 0xbce: /* BOT_B1_U */ case 0xbce: /* BOT_B1_U */
*ret = s->src_f1_bottom >> 16; *ret = s->src_f1_bottom >> 16;
break; break;
case 0xbd0: /* TOP_B2_L */ case 0xbd0: /* TOP_B2_L */
*ret = s->src_f2_top & 0xffff; *ret = s->src_f2_top & 0xffff;
break; break;
case 0xbd2: /* TOP_B2_U */ case 0xbd2: /* TOP_B2_U */
*ret = s->src_f2_top >> 16; *ret = s->src_f2_top >> 16;
break; break;
case 0xbd4: /* BOT_B2_L */ case 0xbd4: /* BOT_B2_L */
*ret = s->src_f2_bottom & 0xffff; *ret = s->src_f2_bottom & 0xffff;
break; break;
case 0xbd6: /* BOT_B2_U */ case 0xbd6: /* BOT_B2_U */
*ret = s->src_f2_bottom >> 16; *ret = s->src_f2_bottom >> 16;
break; break;
case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
*ret = s->element_index_f1; *ret = s->element_index_f1;
break; break;
case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
*ret = s->frame_index_f1 & 0xffff; *ret = s->frame_index_f1 & 0xffff;
break; break;
case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
*ret = s->frame_index_f1 >> 16; *ret = s->frame_index_f1 >> 16;
break; break;
case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
*ret = s->element_index_f2; *ret = s->element_index_f2;
break; break;
case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
*ret = s->frame_index_f2 & 0xffff; *ret = s->frame_index_f2 & 0xffff;
break; break;
case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
*ret = s->frame_index_f2 >> 16; *ret = s->frame_index_f2 >> 16;
break; break;
case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
*ret = s->elements_f1; *ret = s->elements_f1;
break; break;
case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
*ret = s->frames_f1; *ret = s->frames_f1;
break; break;
case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
*ret = s->elements_f2; *ret = s->elements_f2;
break; break;
case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
*ret = s->frames_f2; *ret = s->frames_f2;
break; break;
case 0xbea: /* DMA_LCD_LCH_CTRL */ case 0xbea: /* DMA_LCD_LCH_CTRL */
*ret = s->lch_type; *ret = s->lch_type;
break; break;
@ -1249,7 +1249,7 @@ static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
uint16_t value) uint16_t value)
{ {
switch (offset) { switch (offset) {
case 0x300: /* SYS_DMA_LCD_CTRL */ case 0x300: /* SYS_DMA_LCD_CTRL */
s->src = (value & 0x40) ? imif : emiff; s->src = (value & 0x40) ? imif : emiff;
s->condition = 0; s->condition = 0;
/* Assume no bus errors and thus no BUS_ERROR irq bits. */ /* Assume no bus errors and thus no BUS_ERROR irq bits. */
@ -1257,42 +1257,42 @@ static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
s->dual = value & 1; s->dual = value & 1;
break; break;
case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
s->src_f1_top &= 0xffff0000; s->src_f1_top &= 0xffff0000;
s->src_f1_top |= 0x0000ffff & value; s->src_f1_top |= 0x0000ffff & value;
break; break;
case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
s->src_f1_top &= 0x0000ffff; s->src_f1_top &= 0x0000ffff;
s->src_f1_top |= (uint32_t)value << 16; s->src_f1_top |= (uint32_t)value << 16;
break; break;
case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
s->src_f1_bottom &= 0xffff0000; s->src_f1_bottom &= 0xffff0000;
s->src_f1_bottom |= 0x0000ffff & value; s->src_f1_bottom |= 0x0000ffff & value;
break; break;
case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
s->src_f1_bottom &= 0x0000ffff; s->src_f1_bottom &= 0x0000ffff;
s->src_f1_bottom |= (uint32_t)value << 16; s->src_f1_bottom |= (uint32_t)value << 16;
break; break;
case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
s->src_f2_top &= 0xffff0000; s->src_f2_top &= 0xffff0000;
s->src_f2_top |= 0x0000ffff & value; s->src_f2_top |= 0x0000ffff & value;
break; break;
case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
s->src_f2_top &= 0x0000ffff; s->src_f2_top &= 0x0000ffff;
s->src_f2_top |= (uint32_t)value << 16; s->src_f2_top |= (uint32_t)value << 16;
break; break;
case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
s->src_f2_bottom &= 0xffff0000; s->src_f2_bottom &= 0xffff0000;
s->src_f2_bottom |= 0x0000ffff & value; s->src_f2_bottom |= 0x0000ffff & value;
break; break;
case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
s->src_f2_bottom &= 0x0000ffff; s->src_f2_bottom &= 0x0000ffff;
s->src_f2_bottom |= (uint32_t)value << 16; s->src_f2_bottom |= (uint32_t)value << 16;
break; break;
@ -1309,7 +1309,7 @@ static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
int i; int i;
switch (offset) { switch (offset) {
case 0x300: /* SYS_DMA_LCD_CTRL */ case 0x300: /* SYS_DMA_LCD_CTRL */
i = s->condition; i = s->condition;
s->condition = 0; s->condition = 0;
qemu_irq_lower(s->irq); qemu_irq_lower(s->irq);
@ -1317,35 +1317,35 @@ static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
(s->interrupts << 1) | s->dual; (s->interrupts << 1) | s->dual;
break; break;
case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
*ret = s->src_f1_top & 0xffff; *ret = s->src_f1_top & 0xffff;
break; break;
case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
*ret = s->src_f1_top >> 16; *ret = s->src_f1_top >> 16;
break; break;
case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
*ret = s->src_f1_bottom & 0xffff; *ret = s->src_f1_bottom & 0xffff;
break; break;
case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
*ret = s->src_f1_bottom >> 16; *ret = s->src_f1_bottom >> 16;
break; break;
case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
*ret = s->src_f2_top & 0xffff; *ret = s->src_f2_top & 0xffff;
break; break;
case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
*ret = s->src_f2_top >> 16; *ret = s->src_f2_top >> 16;
break; break;
case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
*ret = s->src_f2_bottom & 0xffff; *ret = s->src_f2_bottom & 0xffff;
break; break;
case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
*ret = s->src_f2_bottom >> 16; *ret = s->src_f2_bottom >> 16;
break; break;
@ -1358,18 +1358,18 @@ static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value) static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value)
{ {
switch (offset) { switch (offset) {
case 0x400: /* SYS_DMA_GCR */ case 0x400: /* SYS_DMA_GCR */
s->gcr = value; s->gcr = value;
break; break;
case 0x404: /* DMA_GSCR */ case 0x404: /* DMA_GSCR */
if (value & 0x8) if (value & 0x8)
omap_dma_disable_3_1_mapping(s); omap_dma_disable_3_1_mapping(s);
else else
omap_dma_enable_3_1_mapping(s); omap_dma_enable_3_1_mapping(s);
break; break;
case 0x408: /* DMA_GRST */ case 0x408: /* DMA_GRST */
if (value & 0x1) if (value & 0x1)
omap_dma_reset(s->dma); omap_dma_reset(s->dma);
break; break;
@ -1384,57 +1384,57 @@ static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
uint16_t *ret) uint16_t *ret)
{ {
switch (offset) { switch (offset) {
case 0x400: /* SYS_DMA_GCR */ case 0x400: /* SYS_DMA_GCR */
*ret = s->gcr; *ret = s->gcr;
break; break;
case 0x404: /* DMA_GSCR */ case 0x404: /* DMA_GSCR */
*ret = s->omap_3_1_mapping_disabled << 3; *ret = s->omap_3_1_mapping_disabled << 3;
break; break;
case 0x408: /* DMA_GRST */ case 0x408: /* DMA_GRST */
*ret = 0; *ret = 0;
break; break;
case 0x442: /* DMA_HW_ID */ case 0x442: /* DMA_HW_ID */
case 0x444: /* DMA_PCh2_ID */ case 0x444: /* DMA_PCh2_ID */
case 0x446: /* DMA_PCh0_ID */ case 0x446: /* DMA_PCh0_ID */
case 0x448: /* DMA_PCh1_ID */ case 0x448: /* DMA_PCh1_ID */
case 0x44a: /* DMA_PChG_ID */ case 0x44a: /* DMA_PChG_ID */
case 0x44c: /* DMA_PChD_ID */ case 0x44c: /* DMA_PChD_ID */
*ret = 1; *ret = 1;
break; break;
case 0x44e: /* DMA_CAPS_0_U */ case 0x44e: /* DMA_CAPS_0_U */
*ret = (s->caps[0] >> 16) & 0xffff; *ret = (s->caps[0] >> 16) & 0xffff;
break; break;
case 0x450: /* DMA_CAPS_0_L */ case 0x450: /* DMA_CAPS_0_L */
*ret = (s->caps[0] >> 0) & 0xffff; *ret = (s->caps[0] >> 0) & 0xffff;
break; break;
case 0x452: /* DMA_CAPS_1_U */ case 0x452: /* DMA_CAPS_1_U */
*ret = (s->caps[1] >> 16) & 0xffff; *ret = (s->caps[1] >> 16) & 0xffff;
break; break;
case 0x454: /* DMA_CAPS_1_L */ case 0x454: /* DMA_CAPS_1_L */
*ret = (s->caps[1] >> 0) & 0xffff; *ret = (s->caps[1] >> 0) & 0xffff;
break; break;
case 0x456: /* DMA_CAPS_2 */ case 0x456: /* DMA_CAPS_2 */
*ret = s->caps[2]; *ret = s->caps[2];
break; break;
case 0x458: /* DMA_CAPS_3 */ case 0x458: /* DMA_CAPS_3 */
*ret = s->caps[3]; *ret = s->caps[3];
break; break;
case 0x45a: /* DMA_CAPS_4 */ case 0x45a: /* DMA_CAPS_4 */
*ret = s->caps[4]; *ret = s->caps[4];
break; break;
case 0x460: /* DMA_PCh2_SR */ case 0x460: /* DMA_PCh2_SR */
case 0x480: /* DMA_PCh0_SR */ case 0x480: /* DMA_PCh0_SR */
case 0x482: /* DMA_PCh1_SR */ case 0x482: /* DMA_PCh1_SR */
case 0x4c0: /* DMA_PChD_SR_0 */ case 0x4c0: /* DMA_PChD_SR_0 */
qemu_log_mask(LOG_UNIMP, qemu_log_mask(LOG_UNIMP,
"%s: Physical Channel Status Registers not implemented\n", "%s: Physical Channel Status Registers not implemented\n",
__func__); __func__);
@ -1582,38 +1582,38 @@ static void omap_dma_setcaps(struct omap_dma_s *s)
case omap_dma_3_2: case omap_dma_3_2:
/* XXX Only available for sDMA */ /* XXX Only available for sDMA */
s->caps[0] = s->caps[0] =
(1 << 19) | /* Constant Fill Capability */ (1 << 19) | /* Constant Fill Capability */
(1 << 18); /* Transparent BLT Capability */ (1 << 18); /* Transparent BLT Capability */
s->caps[1] = s->caps[1] =
(1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */ (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */
s->caps[2] = s->caps[2] =
(1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */ (1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */
(1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */ (1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */
(1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */ (1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */
(1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */ (1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */
(1 << 4) | /* DST_CONST_ADRS_CPBLTY */ (1 << 4) | /* DST_CONST_ADRS_CPBLTY */
(1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */ (1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */
(1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */ (1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */
(1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */ (1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */
(1 << 0); /* SRC_CONST_ADRS_CPBLTY */ (1 << 0); /* SRC_CONST_ADRS_CPBLTY */
s->caps[3] = s->caps[3] =
(1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */ (1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */
(1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */ (1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */
(1 << 5) | /* CHANNEL_CHAINING_CPBLTY */ (1 << 5) | /* CHANNEL_CHAINING_CPBLTY */
(1 << 4) | /* LCh_INTERLEAVE_CPBLTY */ (1 << 4) | /* LCh_INTERLEAVE_CPBLTY */
(1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */ (1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */
(1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */ (1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */
(1 << 1) | /* FRAME_SYNCHR_CPBLTY */ (1 << 1) | /* FRAME_SYNCHR_CPBLTY */
(1 << 0); /* ELMNT_SYNCHR_CPBLTY */ (1 << 0); /* ELMNT_SYNCHR_CPBLTY */
s->caps[4] = s->caps[4] =
(1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */ (1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */
(1 << 6) | /* SYNC_STATUS_CPBLTY */ (1 << 6) | /* SYNC_STATUS_CPBLTY */
(1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */ (1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */
(1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */ (1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */
(1 << 3) | /* FRAME_INTERRUPT_CPBLTY */ (1 << 3) | /* FRAME_INTERRUPT_CPBLTY */
(1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */ (1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */
(1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */ (1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */
(1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */ (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */
break; break;
} }
} }

28
hw/gpio/omap_gpio.c
View file

@ -80,25 +80,25 @@ static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
} }
switch (offset) { switch (offset) {
case 0x00: /* DATA_INPUT */ case 0x00: /* DATA_INPUT */
return s->inputs & s->pins; return s->inputs & s->pins;
case 0x04: /* DATA_OUTPUT */ case 0x04: /* DATA_OUTPUT */
return s->outputs; return s->outputs;
case 0x08: /* DIRECTION_CONTROL */ case 0x08: /* DIRECTION_CONTROL */
return s->dir; return s->dir;
case 0x0c: /* INTERRUPT_CONTROL */ case 0x0c: /* INTERRUPT_CONTROL */
return s->edge; return s->edge;
case 0x10: /* INTERRUPT_MASK */ case 0x10: /* INTERRUPT_MASK */
return s->mask; return s->mask;
case 0x14: /* INTERRUPT_STATUS */ case 0x14: /* INTERRUPT_STATUS */
return s->ints; return s->ints;
case 0x18: /* PIN_CONTROL (not in OMAP310) */ case 0x18: /* PIN_CONTROL (not in OMAP310) */
OMAP_BAD_REG(addr); OMAP_BAD_REG(addr);
return s->pins; return s->pins;
} }
@ -121,11 +121,11 @@ static void omap_gpio_write(void *opaque, hwaddr addr,
} }
switch (offset) { switch (offset) {
case 0x00: /* DATA_INPUT */ case 0x00: /* DATA_INPUT */
OMAP_RO_REG(addr); OMAP_RO_REG(addr);
return; return;
case 0x04: /* DATA_OUTPUT */ case 0x04: /* DATA_OUTPUT */
diff = (s->outputs ^ value) & ~s->dir; diff = (s->outputs ^ value) & ~s->dir;
s->outputs = value; s->outputs = value;
while ((ln = ctz32(diff)) != 32) { while ((ln = ctz32(diff)) != 32) {
@ -135,7 +135,7 @@ static void omap_gpio_write(void *opaque, hwaddr addr,
} }
break; break;
case 0x08: /* DIRECTION_CONTROL */ case 0x08: /* DIRECTION_CONTROL */
diff = s->outputs & (s->dir ^ value); diff = s->outputs & (s->dir ^ value);
s->dir = value; s->dir = value;
@ -147,21 +147,21 @@ static void omap_gpio_write(void *opaque, hwaddr addr,
} }
break; break;
case 0x0c: /* INTERRUPT_CONTROL */ case 0x0c: /* INTERRUPT_CONTROL */
s->edge = value; s->edge = value;
break; break;
case 0x10: /* INTERRUPT_MASK */ case 0x10: /* INTERRUPT_MASK */
s->mask = value; s->mask = value;
break; break;
case 0x14: /* INTERRUPT_STATUS */ case 0x14: /* INTERRUPT_STATUS */
s->ints &= ~value; s->ints &= ~value;
if (!s->ints) if (!s->ints)
qemu_irq_lower(s->irq); qemu_irq_lower(s->irq);
break; break;
case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */ case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */
OMAP_BAD_REG(addr); OMAP_BAD_REG(addr);
s->pins = value; s->pins = value;
break; break;

178
hw/i2c/omap_i2c.c
View file

@ -55,16 +55,16 @@ struct OMAPI2CState {
uint16_t test; uint16_t test;
}; };
#define OMAP2_INTR_REV 0x34 #define OMAP2_INTR_REV 0x34
#define OMAP2_GC_REV 0x34 #define OMAP2_GC_REV 0x34
static void omap_i2c_interrupts_update(OMAPI2CState *s) static void omap_i2c_interrupts_update(OMAPI2CState *s)
{ {
qemu_set_irq(s->irq, s->stat & s->mask); qemu_set_irq(s->irq, s->stat & s->mask);
if ((s->dma >> 15) & 1) /* RDMA_EN */ if ((s->dma >> 15) & 1) /* RDMA_EN */
qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */ qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */
if ((s->dma >> 7) & 1) /* XDMA_EN */ if ((s->dma >> 7) & 1) /* XDMA_EN */
qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */ qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */
} }
static void omap_i2c_fifo_run(OMAPI2CState *s) static void omap_i2c_fifo_run(OMAPI2CState *s)
@ -74,25 +74,25 @@ static void omap_i2c_fifo_run(OMAPI2CState *s)
if (!i2c_bus_busy(s->bus)) if (!i2c_bus_busy(s->bus))
return; return;
if ((s->control >> 2) & 1) { /* RM */ if ((s->control >> 2) & 1) { /* RM */
if ((s->control >> 1) & 1) { /* STP */ if ((s->control >> 1) & 1) { /* STP */
i2c_end_transfer(s->bus); i2c_end_transfer(s->bus);
s->control &= ~(1 << 1); /* STP */ s->control &= ~(1 << 1); /* STP */
s->count_cur = s->count; s->count_cur = s->count;
s->txlen = 0; s->txlen = 0;
} else if ((s->control >> 9) & 1) { /* TRX */ } else if ((s->control >> 9) & 1) { /* TRX */
while (ack && s->txlen) while (ack && s->txlen)
ack = (i2c_send(s->bus, ack = (i2c_send(s->bus,
(s->fifo >> ((-- s->txlen) << 3)) & (s->fifo >> ((-- s->txlen) << 3)) &
0xff) >= 0); 0xff) >= 0);
s->stat |= 1 << 4; /* XRDY */ s->stat |= 1 << 4; /* XRDY */
} else { } else {
while (s->rxlen < 4) while (s->rxlen < 4)
s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3); s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
s->stat |= 1 << 3; /* RRDY */ s->stat |= 1 << 3; /* RRDY */
} }
} else { } else {
if ((s->control >> 9) & 1) { /* TRX */ if ((s->control >> 9) & 1) { /* TRX */
while (ack && s->count_cur && s->txlen) { while (ack && s->count_cur && s->txlen) {
ack = (i2c_send(s->bus, ack = (i2c_send(s->bus,
(s->fifo >> ((-- s->txlen) << 3)) & (s->fifo >> ((-- s->txlen) << 3)) &
@ -100,12 +100,12 @@ static void omap_i2c_fifo_run(OMAPI2CState *s)
s->count_cur --; s->count_cur --;
} }
if (ack && s->count_cur) if (ack && s->count_cur)
s->stat |= 1 << 4; /* XRDY */ s->stat |= 1 << 4; /* XRDY */
else else
s->stat &= ~(1 << 4); /* XRDY */ s->stat &= ~(1 << 4); /* XRDY */
if (!s->count_cur) { if (!s->count_cur) {
s->stat |= 1 << 2; /* ARDY */ s->stat |= 1 << 2; /* ARDY */
s->control &= ~(1 << 10); /* MST */ s->control &= ~(1 << 10); /* MST */
} }
} else { } else {
while (s->count_cur && s->rxlen < 4) { while (s->count_cur && s->rxlen < 4) {
@ -113,26 +113,26 @@ static void omap_i2c_fifo_run(OMAPI2CState *s)
s->count_cur --; s->count_cur --;
} }
if (s->rxlen) if (s->rxlen)
s->stat |= 1 << 3; /* RRDY */ s->stat |= 1 << 3; /* RRDY */
else else
s->stat &= ~(1 << 3); /* RRDY */ s->stat &= ~(1 << 3); /* RRDY */
} }
if (!s->count_cur) { if (!s->count_cur) {
if ((s->control >> 1) & 1) { /* STP */ if ((s->control >> 1) & 1) { /* STP */
i2c_end_transfer(s->bus); i2c_end_transfer(s->bus);
s->control &= ~(1 << 1); /* STP */ s->control &= ~(1 << 1); /* STP */
s->count_cur = s->count; s->count_cur = s->count;
s->txlen = 0; s->txlen = 0;
} else { } else {
s->stat |= 1 << 2; /* ARDY */ s->stat |= 1 << 2; /* ARDY */
s->control &= ~(1 << 10); /* MST */ s->control &= ~(1 << 10); /* MST */
} }
} }
} }
s->stat |= (!ack) << 1; /* NACK */ s->stat |= (!ack) << 1; /* NACK */
if (!ack) if (!ack)
s->control &= ~(1 << 1); /* STP */ s->control &= ~(1 << 1); /* STP */
} }
static void omap_i2c_reset(DeviceState *dev) static void omap_i2c_reset(DeviceState *dev)
@ -163,16 +163,16 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
uint16_t ret; uint16_t ret;
switch (offset) { switch (offset) {
case 0x00: /* I2C_REV */ case 0x00: /* I2C_REV */
return s->revision; /* REV */ return s->revision; /* REV */
case 0x04: /* I2C_IE */ case 0x04: /* I2C_IE */
return s->mask; return s->mask;
case 0x08: /* I2C_STAT */ case 0x08: /* I2C_STAT */
return s->stat | (i2c_bus_busy(s->bus) << 12); return s->stat | (i2c_bus_busy(s->bus) << 12);
case 0x0c: /* I2C_IV */ case 0x0c: /* I2C_IV */
if (s->revision >= OMAP2_INTR_REV) if (s->revision >= OMAP2_INTR_REV)
break; break;
ret = ctz32(s->stat & s->mask); ret = ctz32(s->stat & s->mask);
@ -185,18 +185,18 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
omap_i2c_interrupts_update(s); omap_i2c_interrupts_update(s);
return ret; return ret;
case 0x10: /* I2C_SYSS */ case 0x10: /* I2C_SYSS */
return (s->control >> 15) & 1; /* I2C_EN */ return (s->control >> 15) & 1; /* I2C_EN */
case 0x14: /* I2C_BUF */ case 0x14: /* I2C_BUF */
return s->dma; return s->dma;
case 0x18: /* I2C_CNT */ case 0x18: /* I2C_CNT */
return s->count_cur; /* DCOUNT */ return s->count_cur; /* DCOUNT */
case 0x1c: /* I2C_DATA */ case 0x1c: /* I2C_DATA */
ret = 0; ret = 0;
if (s->control & (1 << 14)) { /* BE */ if (s->control & (1 << 14)) { /* BE */
ret |= ((s->fifo >> 0) & 0xff) << 8; ret |= ((s->fifo >> 0) & 0xff) << 8;
ret |= ((s->fifo >> 8) & 0xff) << 0; ret |= ((s->fifo >> 8) & 0xff) << 0;
} else { } else {
@ -204,7 +204,7 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
ret |= ((s->fifo >> 0) & 0xff) << 0; ret |= ((s->fifo >> 0) & 0xff) << 0;
} }
if (s->rxlen == 1) { if (s->rxlen == 1) {
s->stat |= 1 << 15; /* SBD */ s->stat |= 1 << 15; /* SBD */
s->rxlen = 0; s->rxlen = 0;
} else if (s->rxlen > 1) { } else if (s->rxlen > 1) {
if (s->rxlen > 2) if (s->rxlen > 2)
@ -214,41 +214,41 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
/* XXX: remote access (qualifier) error - what's that? */ /* XXX: remote access (qualifier) error - what's that? */
} }
if (!s->rxlen) { if (!s->rxlen) {
s->stat &= ~(1 << 3); /* RRDY */ s->stat &= ~(1 << 3); /* RRDY */
if (((s->control >> 10) & 1) && /* MST */ if (((s->control >> 10) & 1) && /* MST */
((~s->control >> 9) & 1)) { /* TRX */ ((~s->control >> 9) & 1)) { /* TRX */
s->stat |= 1 << 2; /* ARDY */ s->stat |= 1 << 2; /* ARDY */
s->control &= ~(1 << 10); /* MST */ s->control &= ~(1 << 10); /* MST */
} }
} }
s->stat &= ~(1 << 11); /* ROVR */ s->stat &= ~(1 << 11); /* ROVR */
omap_i2c_fifo_run(s); omap_i2c_fifo_run(s);
omap_i2c_interrupts_update(s); omap_i2c_interrupts_update(s);
return ret; return ret;
case 0x20: /* I2C_SYSC */ case 0x20: /* I2C_SYSC */
return 0; return 0;
case 0x24: /* I2C_CON */ case 0x24: /* I2C_CON */
return s->control; return s->control;
case 0x28: /* I2C_OA */ case 0x28: /* I2C_OA */
return s->addr[0]; return s->addr[0];
case 0x2c: /* I2C_SA */ case 0x2c: /* I2C_SA */
return s->addr[1]; return s->addr[1];
case 0x30: /* I2C_PSC */ case 0x30: /* I2C_PSC */
return s->divider; return s->divider;
case 0x34: /* I2C_SCLL */ case 0x34: /* I2C_SCLL */
return s->times[0]; return s->times[0];
case 0x38: /* I2C_SCLH */ case 0x38: /* I2C_SCLH */
return s->times[1]; return s->times[1];
case 0x3c: /* I2C_SYSTEST */ case 0x3c: /* I2C_SYSTEST */
if (s->test & (1 << 15)) { /* ST_EN */ if (s->test & (1 << 15)) { /* ST_EN */
s->test ^= 0xa; s->test ^= 0xa;
return s->test; return s->test;
} else } else
@ -267,17 +267,17 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
int nack; int nack;
switch (offset) { switch (offset) {
case 0x00: /* I2C_REV */ case 0x00: /* I2C_REV */
case 0x0c: /* I2C_IV */ case 0x0c: /* I2C_IV */
case 0x10: /* I2C_SYSS */ case 0x10: /* I2C_SYSS */
OMAP_RO_REG(addr); OMAP_RO_REG(addr);
return; return;
case 0x04: /* I2C_IE */ case 0x04: /* I2C_IE */
s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f); s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f);
break; break;
case 0x08: /* I2C_STAT */ case 0x08: /* I2C_STAT */
if (s->revision < OMAP2_INTR_REV) { if (s->revision < OMAP2_INTR_REV) {
OMAP_RO_REG(addr); OMAP_RO_REG(addr);
return; return;
@ -288,40 +288,40 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
omap_i2c_interrupts_update(s); omap_i2c_interrupts_update(s);
break; break;
case 0x14: /* I2C_BUF */ case 0x14: /* I2C_BUF */
s->dma = value & 0x8080; s->dma = value & 0x8080;
if (value & (1 << 15)) /* RDMA_EN */ if (value & (1 << 15)) /* RDMA_EN */
s->mask &= ~(1 << 3); /* RRDY_IE */ s->mask &= ~(1 << 3); /* RRDY_IE */
if (value & (1 << 7)) /* XDMA_EN */ if (value & (1 << 7)) /* XDMA_EN */
s->mask &= ~(1 << 4); /* XRDY_IE */ s->mask &= ~(1 << 4); /* XRDY_IE */
break; break;
case 0x18: /* I2C_CNT */ case 0x18: /* I2C_CNT */
s->count = value; /* DCOUNT */ s->count = value; /* DCOUNT */
break; break;
case 0x1c: /* I2C_DATA */ case 0x1c: /* I2C_DATA */
if (s->txlen > 2) { if (s->txlen > 2) {
/* XXX: remote access (qualifier) error - what's that? */ /* XXX: remote access (qualifier) error - what's that? */
break; break;
} }
s->fifo <<= 16; s->fifo <<= 16;
s->txlen += 2; s->txlen += 2;
if (s->control & (1 << 14)) { /* BE */ if (s->control & (1 << 14)) { /* BE */
s->fifo |= ((value >> 8) & 0xff) << 8; s->fifo |= ((value >> 8) & 0xff) << 8;
s->fifo |= ((value >> 0) & 0xff) << 0; s->fifo |= ((value >> 0) & 0xff) << 0;
} else { } else {
s->fifo |= ((value >> 0) & 0xff) << 8; s->fifo |= ((value >> 0) & 0xff) << 8;
s->fifo |= ((value >> 8) & 0xff) << 0; s->fifo |= ((value >> 8) & 0xff) << 0;
} }
s->stat &= ~(1 << 10); /* XUDF */ s->stat &= ~(1 << 10); /* XUDF */
if (s->txlen > 2) if (s->txlen > 2)
s->stat &= ~(1 << 4); /* XRDY */ s->stat &= ~(1 << 4); /* XRDY */
omap_i2c_fifo_run(s); omap_i2c_fifo_run(s);
omap_i2c_interrupts_update(s); omap_i2c_interrupts_update(s);
break; break;
case 0x20: /* I2C_SYSC */ case 0x20: /* I2C_SYSC */
if (s->revision < OMAP2_INTR_REV) { if (s->revision < OMAP2_INTR_REV) {
OMAP_BAD_REG(addr); OMAP_BAD_REG(addr);
return; return;
@ -332,9 +332,9 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
} }
break; break;
case 0x24: /* I2C_CON */ case 0x24: /* I2C_CON */
s->control = value & 0xcf87; s->control = value & 0xcf87;
if (~value & (1 << 15)) { /* I2C_EN */ if (~value & (1 << 15)) { /* I2C_EN */
if (s->revision < OMAP2_INTR_REV) { if (s->revision < OMAP2_INTR_REV) {
omap_i2c_reset(DEVICE(s)); omap_i2c_reset(DEVICE(s));
} }
@ -351,14 +351,14 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
__func__); __func__);
break; break;
} }
if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */ if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */
nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */ nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */
(~value >> 9) & 1); /* TRX */ (~value >> 9) & 1); /* TRX */
s->stat |= nack << 1; /* NACK */ s->stat |= nack << 1; /* NACK */
s->control &= ~(1 << 0); /* STT */ s->control &= ~(1 << 0); /* STT */
s->fifo = 0; s->fifo = 0;
if (nack) if (nack)
s->control &= ~(1 << 1); /* STP */ s->control &= ~(1 << 1); /* STP */
else { else {
s->count_cur = s->count; s->count_cur = s->count;
omap_i2c_fifo_run(s); omap_i2c_fifo_run(s);
@ -367,34 +367,34 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
} }
break; break;
case 0x28: /* I2C_OA */ case 0x28: /* I2C_OA */
s->addr[0] = value & 0x3ff; s->addr[0] = value & 0x3ff;
break; break;
case 0x2c: /* I2C_SA */ case 0x2c: /* I2C_SA */
s->addr[1] = value & 0x3ff; s->addr[1] = value & 0x3ff;
break; break;
case 0x30: /* I2C_PSC */ case 0x30: /* I2C_PSC */
s->divider = value; s->divider = value;
break; break;
case 0x34: /* I2C_SCLL */ case 0x34: /* I2C_SCLL */
s->times[0] = value; s->times[0] = value;
break; break;
case 0x38: /* I2C_SCLH */ case 0x38: /* I2C_SCLH */
s->times[1] = value; s->times[1] = value;
break; break;
case 0x3c: /* I2C_SYSTEST */ case 0x3c: /* I2C_SYSTEST */
s->test = value & 0xf80f; s->test = value & 0xf80f;
if (value & (1 << 11)) /* SBB */ if (value & (1 << 11)) /* SBB */
if (s->revision >= OMAP2_INTR_REV) { if (s->revision >= OMAP2_INTR_REV) {
s->stat |= 0x3f; s->stat |= 0x3f;
omap_i2c_interrupts_update(s); omap_i2c_interrupts_update(s);
} }
if (value & (1 << 15)) { /* ST_EN */ if (value & (1 << 15)) { /* ST_EN */
qemu_log_mask(LOG_UNIMP, qemu_log_mask(LOG_UNIMP,
"%s: System Test not supported\n", __func__); "%s: System Test not supported\n", __func__);
} }
@ -413,7 +413,7 @@ static void omap_i2c_writeb(void *opaque, hwaddr addr,
int offset = addr & OMAP_MPUI_REG_MASK; int offset = addr & OMAP_MPUI_REG_MASK;
switch (offset) { switch (offset) {
case 0x1c: /* I2C_DATA */ case 0x1c: /* I2C_DATA */
if (s->txlen > 2) { if (s->txlen > 2) {
/* XXX: remote access (qualifier) error - what's that? */ /* XXX: remote access (qualifier) error - what's that? */
break; break;
@ -421,9 +421,9 @@ static void omap_i2c_writeb(void *opaque, hwaddr addr,
s->fifo <<= 8; s->fifo <<= 8;
s->txlen += 1; s->txlen += 1;
s->fifo |= value & 0xff; s->fifo |= value & 0xff;
s->stat &= ~(1 << 10); /* XUDF */ s->stat &= ~(1 << 10); /* XUDF */
if (s->txlen > 2) if (s->txlen > 2)
s->stat &= ~(1 << 4); /* XRDY */ s->stat &= ~(1 << 4); /* XRDY */
omap_i2c_fifo_run(s); omap_i2c_fifo_run(s);
omap_i2c_interrupts_update(s); omap_i2c_interrupts_update(s);
break; break;

154
hw/intc/omap_intc.c
View file

@ -102,8 +102,8 @@ static inline void omap_inth_update(OMAPIntcState *s, int is_fiq)
} }
} }
#define INT_FALLING_EDGE 0 #define INT_FALLING_EDGE 0
#define INT_LOW_LEVEL 1 #define INT_LOW_LEVEL 1
static void omap_set_intr(void *opaque, int irq, int req) static void omap_set_intr(void *opaque, int irq, int req)
{ {
@ -142,13 +142,13 @@ static uint64_t omap_inth_read(void *opaque, hwaddr addr,
offset &= 0xff; offset &= 0xff;
switch (offset) { switch (offset) {
case 0x00: /* ITR */ case 0x00: /* ITR */
return bank->irqs; return bank->irqs;
case 0x04: /* MIR */ case 0x04: /* MIR */
return bank->mask; return bank->mask;
case 0x10: /* SIR_IRQ_CODE */ case 0x10: /* SIR_IRQ_CODE */
case 0x14: /* SIR_FIQ_CODE */ case 0x14: /* SIR_FIQ_CODE */
if (bank_no != 0) if (bank_no != 0)
break; break;
@ -159,49 +159,49 @@ static uint64_t omap_inth_read(void *opaque, hwaddr addr,
bank->irqs &= ~(1 << i); bank->irqs &= ~(1 << i);
return line_no; return line_no;
case 0x18: /* CONTROL_REG */ case 0x18: /* CONTROL_REG */
if (bank_no != 0) if (bank_no != 0)
break; break;
return 0; return 0;
case 0x1c: /* ILR0 */ case 0x1c: /* ILR0 */
case 0x20: /* ILR1 */ case 0x20: /* ILR1 */
case 0x24: /* ILR2 */ case 0x24: /* ILR2 */
case 0x28: /* ILR3 */ case 0x28: /* ILR3 */
case 0x2c: /* ILR4 */ case 0x2c: /* ILR4 */
case 0x30: /* ILR5 */ case 0x30: /* ILR5 */
case 0x34: /* ILR6 */ case 0x34: /* ILR6 */
case 0x38: /* ILR7 */ case 0x38: /* ILR7 */
case 0x3c: /* ILR8 */ case 0x3c: /* ILR8 */
case 0x40: /* ILR9 */ case 0x40: /* ILR9 */
case 0x44: /* ILR10 */ case 0x44: /* ILR10 */
case 0x48: /* ILR11 */ case 0x48: /* ILR11 */
case 0x4c: /* ILR12 */ case 0x4c: /* ILR12 */
case 0x50: /* ILR13 */ case 0x50: /* ILR13 */
case 0x54: /* ILR14 */ case 0x54: /* ILR14 */
case 0x58: /* ILR15 */ case 0x58: /* ILR15 */
case 0x5c: /* ILR16 */ case 0x5c: /* ILR16 */
case 0x60: /* ILR17 */ case 0x60: /* ILR17 */
case 0x64: /* ILR18 */ case 0x64: /* ILR18 */
case 0x68: /* ILR19 */ case 0x68: /* ILR19 */
case 0x6c: /* ILR20 */ case 0x6c: /* ILR20 */
case 0x70: /* ILR21 */ case 0x70: /* ILR21 */
case 0x74: /* ILR22 */ case 0x74: /* ILR22 */
case 0x78: /* ILR23 */ case 0x78: /* ILR23 */
case 0x7c: /* ILR24 */ case 0x7c: /* ILR24 */
case 0x80: /* ILR25 */ case 0x80: /* ILR25 */
case 0x84: /* ILR26 */ case 0x84: /* ILR26 */
case 0x88: /* ILR27 */ case 0x88: /* ILR27 */
case 0x8c: /* ILR28 */ case 0x8c: /* ILR28 */
case 0x90: /* ILR29 */ case 0x90: /* ILR29 */
case 0x94: /* ILR30 */ case 0x94: /* ILR30 */
case 0x98: /* ILR31 */ case 0x98: /* ILR31 */
i = (offset - 0x1c) >> 2; i = (offset - 0x1c) >> 2;
return (bank->priority[i] << 2) | return (bank->priority[i] << 2) |
(((bank->sens_edge >> i) & 1) << 1) | (((bank->sens_edge >> i) & 1) << 1) |
((bank->fiq >> i) & 1); ((bank->fiq >> i) & 1);
case 0x9c: /* ISR */ case 0x9c: /* ISR */
return 0x00000000; return 0x00000000;
} }
@ -219,24 +219,24 @@ static void omap_inth_write(void *opaque, hwaddr addr,
offset &= 0xff; offset &= 0xff;
switch (offset) { switch (offset) {
case 0x00: /* ITR */ case 0x00: /* ITR */
/* Important: ignore the clearing if the IRQ is level-triggered and /* Important: ignore the clearing if the IRQ is level-triggered and
the input bit is 1 */ the input bit is 1 */
bank->irqs &= value | (bank->inputs & bank->sens_edge); bank->irqs &= value | (bank->inputs & bank->sens_edge);
return; return;
case 0x04: /* MIR */ case 0x04: /* MIR */
bank->mask = value; bank->mask = value;
omap_inth_update(s, 0); omap_inth_update(s, 0);
omap_inth_update(s, 1); omap_inth_update(s, 1);
return; return;
case 0x10: /* SIR_IRQ_CODE */ case 0x10: /* SIR_IRQ_CODE */
case 0x14: /* SIR_FIQ_CODE */ case 0x14: /* SIR_FIQ_CODE */
OMAP_RO_REG(addr); OMAP_RO_REG(addr);
break; break;
case 0x18: /* CONTROL_REG */ case 0x18: /* CONTROL_REG */
if (bank_no != 0) if (bank_no != 0)
break; break;
if (value & 2) { if (value & 2) {
@ -251,38 +251,38 @@ static void omap_inth_write(void *opaque, hwaddr addr,
} }
return; return;
case 0x1c: /* ILR0 */ case 0x1c: /* ILR0 */
case 0x20: /* ILR1 */ case 0x20: /* ILR1 */
case 0x24: /* ILR2 */ case 0x24: /* ILR2 */
case 0x28: /* ILR3 */ case 0x28: /* ILR3 */
case 0x2c: /* ILR4 */ case 0x2c: /* ILR4 */
case 0x30: /* ILR5 */ case 0x30: /* ILR5 */
case 0x34: /* ILR6 */ case 0x34: /* ILR6 */
case 0x38: /* ILR7 */ case 0x38: /* ILR7 */
case 0x3c: /* ILR8 */ case 0x3c: /* ILR8 */
case 0x40: /* ILR9 */ case 0x40: /* ILR9 */
case 0x44: /* ILR10 */ case 0x44: /* ILR10 */
case 0x48: /* ILR11 */ case 0x48: /* ILR11 */
case 0x4c: /* ILR12 */ case 0x4c: /* ILR12 */
case 0x50: /* ILR13 */ case 0x50: /* ILR13 */
case 0x54: /* ILR14 */ case 0x54: /* ILR14 */
case 0x58: /* ILR15 */ case 0x58: /* ILR15 */
case 0x5c: /* ILR16 */ case 0x5c: /* ILR16 */
case 0x60: /* ILR17 */ case 0x60: /* ILR17 */
case 0x64: /* ILR18 */ case 0x64: /* ILR18 */
case 0x68: /* ILR19 */ case 0x68: /* ILR19 */
case 0x6c: /* ILR20 */ case 0x6c: /* ILR20 */
case 0x70: /* ILR21 */ case 0x70: /* ILR21 */
case 0x74: /* ILR22 */ case 0x74: /* ILR22 */
case 0x78: /* ILR23 */ case 0x78: /* ILR23 */
case 0x7c: /* ILR24 */ case 0x7c: /* ILR24 */
case 0x80: /* ILR25 */ case 0x80: /* ILR25 */
case 0x84: /* ILR26 */ case 0x84: /* ILR26 */
case 0x88: /* ILR27 */ case 0x88: /* ILR27 */
case 0x8c: /* ILR28 */ case 0x8c: /* ILR28 */
case 0x90: /* ILR29 */ case 0x90: /* ILR29 */
case 0x94: /* ILR30 */ case 0x94: /* ILR30 */
case 0x98: /* ILR31 */ case 0x98: /* ILR31 */
i = (offset - 0x1c) >> 2; i = (offset - 0x1c) >> 2;
bank->priority[i] = (value >> 2) & 0x1f; bank->priority[i] = (value >> 2) & 0x1f;
bank->sens_edge &= ~(1 << i); bank->sens_edge &= ~(1 << i);
@ -291,7 +291,7 @@ static void omap_inth_write(void *opaque, hwaddr addr,
bank->fiq |= (value & 1) << i; bank->fiq |= (value & 1) << i;
return; return;
case 0x9c: /* ISR */ case 0x9c: /* ISR */
for (i = 0; i < 32; i ++) for (i = 0; i < 32; i ++)
if (value & (1 << i)) { if (value & (1 << i)) {
omap_set_intr(s, 32 * bank_no + i, 1); omap_set_intr(s, 32 * bank_no + i, 1);

470
hw/misc/omap_clk.c
View file

@ -30,170 +30,170 @@ struct clk {
struct clk *parent; struct clk *parent;
struct clk *child1; struct clk *child1;
struct clk *sibling; struct clk *sibling;
#define ALWAYS_ENABLED (1 << 0) #define ALWAYS_ENABLED (1 << 0)
#define CLOCK_IN_OMAP310 (1 << 10) #define CLOCK_IN_OMAP310 (1 << 10)
#define CLOCK_IN_OMAP730 (1 << 11) #define CLOCK_IN_OMAP730 (1 << 11)
#define CLOCK_IN_OMAP1510 (1 << 12) #define CLOCK_IN_OMAP1510 (1 << 12)
#define CLOCK_IN_OMAP16XX (1 << 13) #define CLOCK_IN_OMAP16XX (1 << 13)
uint32_t flags; uint32_t flags;
int id; int id;
int running; /* Is currently ticking */ int running; /* Is currently ticking */
int enabled; /* Is enabled, regardless of its input clk */ int enabled; /* Is enabled, regardless of its input clk */
unsigned long rate; /* Current rate (if .running) */ unsigned long rate; /* Current rate (if .running) */
unsigned int divisor; /* Rate relative to input (if .enabled) */ unsigned int divisor; /* Rate relative to input (if .enabled) */
unsigned int multiplier; /* Rate relative to input (if .enabled) */ unsigned int multiplier; /* Rate relative to input (if .enabled) */
qemu_irq users[16]; /* Who to notify on change */ qemu_irq users[16]; /* Who to notify on change */
int usecount; /* Automatically idle when unused */ int usecount; /* Automatically idle when unused */
}; };
static struct clk xtal_osc12m = { static struct clk xtal_osc12m = {
.name = "xtal_osc_12m", .name = "xtal_osc_12m",
.rate = 12000000, .rate = 12000000,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
}; };
static struct clk xtal_osc32k = { static struct clk xtal_osc32k = {
.name = "xtal_osc_32k", .name = "xtal_osc_32k",
.rate = 32768, .rate = 32768,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
}; };
static struct clk ck_ref = { static struct clk ck_ref = {
.name = "ck_ref", .name = "ck_ref",
.alias = "clkin", .alias = "clkin",
.parent = &xtal_osc12m, .parent = &xtal_osc12m,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
ALWAYS_ENABLED, ALWAYS_ENABLED,
}; };
/* If a dpll is disabled it becomes a bypass, child clocks don't stop */ /* If a dpll is disabled it becomes a bypass, child clocks don't stop */
static struct clk dpll1 = { static struct clk dpll1 = {
.name = "dpll1", .name = "dpll1",
.parent = &ck_ref, .parent = &ck_ref,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
ALWAYS_ENABLED, ALWAYS_ENABLED,
}; };
static struct clk dpll2 = { static struct clk dpll2 = {
.name = "dpll2", .name = "dpll2",
.parent = &ck_ref, .parent = &ck_ref,
.flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
}; };
static struct clk dpll3 = { static struct clk dpll3 = {
.name = "dpll3", .name = "dpll3",
.parent = &ck_ref, .parent = &ck_ref,
.flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
}; };
static struct clk dpll4 = { static struct clk dpll4 = {
.name = "dpll4", .name = "dpll4",
.parent = &ck_ref, .parent = &ck_ref,
.multiplier = 4, .multiplier = 4,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
}; };
static struct clk apll = { static struct clk apll = {
.name = "apll", .name = "apll",
.parent = &ck_ref, .parent = &ck_ref,
.multiplier = 48, .multiplier = 48,
.divisor = 12, .divisor = 12,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
}; };
static struct clk ck_48m = { static struct clk ck_48m = {
.name = "ck_48m", .name = "ck_48m",
.parent = &dpll4, /* either dpll4 or apll */ .parent = &dpll4, /* either dpll4 or apll */
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
}; };
static struct clk ck_dpll1out = { static struct clk ck_dpll1out = {
.name = "ck_dpll1out", .name = "ck_dpll1out",
.parent = &dpll1, .parent = &dpll1,
.flags = CLOCK_IN_OMAP16XX, .flags = CLOCK_IN_OMAP16XX,
}; };
static struct clk sossi_ck = { static struct clk sossi_ck = {
.name = "ck_sossi", .name = "ck_sossi",
.parent = &ck_dpll1out, .parent = &ck_dpll1out,
.flags = CLOCK_IN_OMAP16XX, .flags = CLOCK_IN_OMAP16XX,
}; };
static struct clk clkm1 = { static struct clk clkm1 = {
.name = "clkm1", .name = "clkm1",
.alias = "ck_gen1", .alias = "ck_gen1",
.parent = &dpll1, .parent = &dpll1,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
ALWAYS_ENABLED, ALWAYS_ENABLED,
}; };
static struct clk clkm2 = { static struct clk clkm2 = {
.name = "clkm2", .name = "clkm2",
.alias = "ck_gen2", .alias = "ck_gen2",
.parent = &dpll1, .parent = &dpll1,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
ALWAYS_ENABLED, ALWAYS_ENABLED,
}; };
static struct clk clkm3 = { static struct clk clkm3 = {
.name = "clkm3", .name = "clkm3",
.alias = "ck_gen3", .alias = "ck_gen3",
.parent = &dpll1, /* either dpll1 or ck_ref */ .parent = &dpll1, /* either dpll1 or ck_ref */
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
ALWAYS_ENABLED, ALWAYS_ENABLED,
}; };
static struct clk arm_ck = { static struct clk arm_ck = {
.name = "arm_ck", .name = "arm_ck",
.alias = "mpu_ck", .alias = "mpu_ck",
.parent = &clkm1, .parent = &clkm1,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
ALWAYS_ENABLED, ALWAYS_ENABLED,
}; };
static struct clk armper_ck = { static struct clk armper_ck = {
.name = "armper_ck", .name = "armper_ck",
.alias = "mpuper_ck", .alias = "mpuper_ck",
.parent = &clkm1, .parent = &clkm1,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
}; };
static struct clk arm_gpio_ck = { static struct clk arm_gpio_ck = {
.name = "arm_gpio_ck", .name = "arm_gpio_ck",
.alias = "mpu_gpio_ck", .alias = "mpu_gpio_ck",
.parent = &clkm1, .parent = &clkm1,
.divisor = 1, .divisor = 1,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
}; };
static struct clk armxor_ck = { static struct clk armxor_ck = {
.name = "armxor_ck", .name = "armxor_ck",
.alias = "mpuxor_ck", .alias = "mpuxor_ck",
.parent = &ck_ref, .parent = &ck_ref,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
}; };
static struct clk armtim_ck = { static struct clk armtim_ck = {
.name = "armtim_ck", .name = "armtim_ck",
.alias = "mputim_ck", .alias = "mputim_ck",
.parent = &ck_ref, /* either CLKIN or DPLL1 */ .parent = &ck_ref, /* either CLKIN or DPLL1 */
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
}; };
static struct clk armwdt_ck = { static struct clk armwdt_ck = {
.name = "armwdt_ck", .name = "armwdt_ck",
.alias = "mpuwd_ck", .alias = "mpuwd_ck",
.parent = &clkm1, .parent = &clkm1,
.divisor = 14, .divisor = 14,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
ALWAYS_ENABLED, ALWAYS_ENABLED,
}; };
static struct clk arminth_ck16xx = { static struct clk arminth_ck16xx = {
.name = "arminth_ck", .name = "arminth_ck",
.parent = &arm_ck, .parent = &arm_ck,
.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
/* Note: On 16xx the frequency can be divided by 2 by programming /* Note: On 16xx the frequency can be divided by 2 by programming
* ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
* *
@ -202,48 +202,48 @@ static struct clk arminth_ck16xx = {
}; };
static struct clk dsp_ck = { static struct clk dsp_ck = {
.name = "dsp_ck", .name = "dsp_ck",
.parent = &clkm2, .parent = &clkm2,
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
}; };
static struct clk dspmmu_ck = { static struct clk dspmmu_ck = {
.name = "dspmmu_ck", .name = "dspmmu_ck",
.parent = &clkm2, .parent = &clkm2,
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
ALWAYS_ENABLED, ALWAYS_ENABLED,
}; };
static struct clk dspper_ck = { static struct clk dspper_ck = {
.name = "dspper_ck", .name = "dspper_ck",
.parent = &clkm2, .parent = &clkm2,
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
}; };
static struct clk dspxor_ck = { static struct clk dspxor_ck = {
.name = "dspxor_ck", .name = "dspxor_ck",
.parent = &ck_ref, .parent = &ck_ref,
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
}; };
static struct clk dsptim_ck = { static struct clk dsptim_ck = {
.name = "dsptim_ck", .name = "dsptim_ck",
.parent = &ck_ref, .parent = &ck_ref,
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
}; };
static struct clk tc_ck = { static struct clk tc_ck = {
.name = "tc_ck", .name = "tc_ck",
.parent = &clkm3, .parent = &clkm3,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 | CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
ALWAYS_ENABLED, ALWAYS_ENABLED,
}; };
static struct clk arminth_ck15xx = { static struct clk arminth_ck15xx = {
.name = "arminth_ck", .name = "arminth_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
/* Note: On 1510 the frequency follows TC_CK /* Note: On 1510 the frequency follows TC_CK
* *
* 16xx version is in MPU clocks. * 16xx version is in MPU clocks.
@ -252,259 +252,259 @@ static struct clk arminth_ck15xx = {
static struct clk tipb_ck = { static struct clk tipb_ck = {
/* No-idle controlled by "tc_ck" */ /* No-idle controlled by "tc_ck" */
.name = "tipb_ck", .name = "tipb_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
}; };
static struct clk l3_ocpi_ck = { static struct clk l3_ocpi_ck = {
/* No-idle controlled by "tc_ck" */ /* No-idle controlled by "tc_ck" */
.name = "l3_ocpi_ck", .name = "l3_ocpi_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = CLOCK_IN_OMAP16XX, .flags = CLOCK_IN_OMAP16XX,
}; };
static struct clk tc1_ck = { static struct clk tc1_ck = {
.name = "tc1_ck", .name = "tc1_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = CLOCK_IN_OMAP16XX, .flags = CLOCK_IN_OMAP16XX,
}; };
static struct clk tc2_ck = { static struct clk tc2_ck = {
.name = "tc2_ck", .name = "tc2_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = CLOCK_IN_OMAP16XX, .flags = CLOCK_IN_OMAP16XX,
}; };
static struct clk dma_ck = { static struct clk dma_ck = {
/* No-idle controlled by "tc_ck" */ /* No-idle controlled by "tc_ck" */
.name = "dma_ck", .name = "dma_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
ALWAYS_ENABLED, ALWAYS_ENABLED,
}; };
static struct clk dma_lcdfree_ck = { static struct clk dma_lcdfree_ck = {
.name = "dma_lcdfree_ck", .name = "dma_lcdfree_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
}; };
static struct clk api_ck = { static struct clk api_ck = {
.name = "api_ck", .name = "api_ck",
.alias = "mpui_ck", .alias = "mpui_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
}; };
static struct clk lb_ck = { static struct clk lb_ck = {
.name = "lb_ck", .name = "lb_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
}; };
static struct clk lbfree_ck = { static struct clk lbfree_ck = {
.name = "lbfree_ck", .name = "lbfree_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
}; };
static struct clk hsab_ck = { static struct clk hsab_ck = {
.name = "hsab_ck", .name = "hsab_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
}; };
static struct clk rhea1_ck = { static struct clk rhea1_ck = {
.name = "rhea1_ck", .name = "rhea1_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
}; };
static struct clk rhea2_ck = { static struct clk rhea2_ck = {
.name = "rhea2_ck", .name = "rhea2_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
}; };
static struct clk lcd_ck_16xx = { static struct clk lcd_ck_16xx = {
.name = "lcd_ck", .name = "lcd_ck",
.parent = &clkm3, .parent = &clkm3,
.flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730, .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730,
}; };
static struct clk lcd_ck_1510 = { static struct clk lcd_ck_1510 = {
.name = "lcd_ck", .name = "lcd_ck",
.parent = &clkm3, .parent = &clkm3,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
}; };
static struct clk uart1_1510 = { static struct clk uart1_1510 = {
.name = "uart1_ck", .name = "uart1_ck",
/* Direct from ULPD, no real parent */ /* Direct from ULPD, no real parent */
.parent = &armper_ck, /* either armper_ck or dpll4 */ .parent = &armper_ck, /* either armper_ck or dpll4 */
.rate = 12000000, .rate = 12000000,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
}; };
static struct clk uart1_16xx = { static struct clk uart1_16xx = {
.name = "uart1_ck", .name = "uart1_ck",
/* Direct from ULPD, no real parent */ /* Direct from ULPD, no real parent */
.parent = &armper_ck, .parent = &armper_ck,
.rate = 48000000, .rate = 48000000,
.flags = CLOCK_IN_OMAP16XX, .flags = CLOCK_IN_OMAP16XX,
}; };
static struct clk uart2_ck = { static struct clk uart2_ck = {
.name = "uart2_ck", .name = "uart2_ck",
/* Direct from ULPD, no real parent */ /* Direct from ULPD, no real parent */
.parent = &armper_ck, /* either armper_ck or dpll4 */ .parent = &armper_ck, /* either armper_ck or dpll4 */
.rate = 12000000, .rate = 12000000,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
ALWAYS_ENABLED, ALWAYS_ENABLED,
}; };
static struct clk uart3_1510 = { static struct clk uart3_1510 = {
.name = "uart3_ck", .name = "uart3_ck",
/* Direct from ULPD, no real parent */ /* Direct from ULPD, no real parent */
.parent = &armper_ck, /* either armper_ck or dpll4 */ .parent = &armper_ck, /* either armper_ck or dpll4 */
.rate = 12000000, .rate = 12000000,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
}; };
static struct clk uart3_16xx = { static struct clk uart3_16xx = {
.name = "uart3_ck", .name = "uart3_ck",
/* Direct from ULPD, no real parent */ /* Direct from ULPD, no real parent */
.parent = &armper_ck, .parent = &armper_ck,
.rate = 48000000, .rate = 48000000,
.flags = CLOCK_IN_OMAP16XX, .flags = CLOCK_IN_OMAP16XX,
}; };
static struct clk usb_clk0 = { /* 6 MHz output on W4_USB_CLK0 */ static struct clk usb_clk0 = { /* 6 MHz output on W4_USB_CLK0 */
.name = "usb_clk0", .name = "usb_clk0",
.alias = "usb.clko", .alias = "usb.clko",
/* Direct from ULPD, no parent */ /* Direct from ULPD, no parent */
.rate = 6000000, .rate = 6000000,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
}; };
static struct clk usb_hhc_ck1510 = { static struct clk usb_hhc_ck1510 = {
.name = "usb_hhc_ck", .name = "usb_hhc_ck",
/* Direct from ULPD, no parent */ /* Direct from ULPD, no parent */
.rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
}; };
static struct clk usb_hhc_ck16xx = { static struct clk usb_hhc_ck16xx = {
.name = "usb_hhc_ck", .name = "usb_hhc_ck",
/* Direct from ULPD, no parent */ /* Direct from ULPD, no parent */
.rate = 48000000, .rate = 48000000,
/* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
.flags = CLOCK_IN_OMAP16XX, .flags = CLOCK_IN_OMAP16XX,
}; };
static struct clk usb_w2fc_mclk = { static struct clk usb_w2fc_mclk = {
.name = "usb_w2fc_mclk", .name = "usb_w2fc_mclk",
.alias = "usb_w2fc_ck", .alias = "usb_w2fc_ck",
.parent = &ck_48m, .parent = &ck_48m,
.rate = 48000000, .rate = 48000000,
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
}; };
static struct clk mclk_1510 = { static struct clk mclk_1510 = {
.name = "mclk", .name = "mclk",
/* Direct from ULPD, no parent. May be enabled by ext hardware. */ /* Direct from ULPD, no parent. May be enabled by ext hardware. */
.rate = 12000000, .rate = 12000000,
.flags = CLOCK_IN_OMAP1510, .flags = CLOCK_IN_OMAP1510,
}; };
static struct clk bclk_310 = { static struct clk bclk_310 = {
.name = "bt_mclk_out", /* Alias midi_mclk_out? */ .name = "bt_mclk_out", /* Alias midi_mclk_out? */
.parent = &armper_ck, .parent = &armper_ck,
.flags = CLOCK_IN_OMAP310, .flags = CLOCK_IN_OMAP310,
}; };
static struct clk mclk_310 = { static struct clk mclk_310 = {
.name = "com_mclk_out", .name = "com_mclk_out",
.parent = &armper_ck, .parent = &armper_ck,
.flags = CLOCK_IN_OMAP310, .flags = CLOCK_IN_OMAP310,
}; };
static struct clk mclk_16xx = { static struct clk mclk_16xx = {
.name = "mclk", .name = "mclk",
/* Direct from ULPD, no parent. May be enabled by ext hardware. */ /* Direct from ULPD, no parent. May be enabled by ext hardware. */
.flags = CLOCK_IN_OMAP16XX, .flags = CLOCK_IN_OMAP16XX,
}; };
static struct clk bclk_1510 = { static struct clk bclk_1510 = {
.name = "bclk", .name = "bclk",
/* Direct from ULPD, no parent. May be enabled by ext hardware. */ /* Direct from ULPD, no parent. May be enabled by ext hardware. */
.rate = 12000000, .rate = 12000000,
.flags = CLOCK_IN_OMAP1510, .flags = CLOCK_IN_OMAP1510,
}; };
static struct clk bclk_16xx = { static struct clk bclk_16xx = {
.name = "bclk", .name = "bclk",
/* Direct from ULPD, no parent. May be enabled by ext hardware. */ /* Direct from ULPD, no parent. May be enabled by ext hardware. */
.flags = CLOCK_IN_OMAP16XX, .flags = CLOCK_IN_OMAP16XX,
}; };
static struct clk mmc1_ck = { static struct clk mmc1_ck = {
.name = "mmc_ck", .name = "mmc_ck",
.id = 1, .id = 1,
/* Functional clock is direct from ULPD, interface clock is ARMPER */ /* Functional clock is direct from ULPD, interface clock is ARMPER */
.parent = &armper_ck, /* either armper_ck or dpll4 */ .parent = &armper_ck, /* either armper_ck or dpll4 */
.rate = 48000000, .rate = 48000000,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
}; };
static struct clk mmc2_ck = { static struct clk mmc2_ck = {
.name = "mmc_ck", .name = "mmc_ck",
.id = 2, .id = 2,
/* Functional clock is direct from ULPD, interface clock is ARMPER */ /* Functional clock is direct from ULPD, interface clock is ARMPER */
.parent = &armper_ck, .parent = &armper_ck,
.rate = 48000000, .rate = 48000000,
.flags = CLOCK_IN_OMAP16XX, .flags = CLOCK_IN_OMAP16XX,
}; };
static struct clk cam_mclk = { static struct clk cam_mclk = {
.name = "cam.mclk", .name = "cam.mclk",
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
.rate = 12000000, .rate = 12000000,
}; };
static struct clk cam_exclk = { static struct clk cam_exclk = {
.name = "cam.exclk", .name = "cam.exclk",
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
/* Either 12M from cam.mclk or 48M from dpll4 */ /* Either 12M from cam.mclk or 48M from dpll4 */
.parent = &cam_mclk, .parent = &cam_mclk,
}; };
static struct clk cam_lclk = { static struct clk cam_lclk = {
.name = "cam.lclk", .name = "cam.lclk",
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
}; };
static struct clk i2c_fck = { static struct clk i2c_fck = {
.name = "i2c_fck", .name = "i2c_fck",
.id = 1, .id = 1,
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
ALWAYS_ENABLED, ALWAYS_ENABLED,
.parent = &armxor_ck, .parent = &armxor_ck,
}; };
static struct clk i2c_ick = { static struct clk i2c_ick = {
.name = "i2c_ick", .name = "i2c_ick",
.id = 1, .id = 1,
.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
.parent = &armper_ck, .parent = &armper_ck,
}; };
static struct clk clk32k = { static struct clk clk32k = {
.name = "clk32-kHz", .name = "clk32-kHz",
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
ALWAYS_ENABLED, ALWAYS_ENABLED,
.parent = &xtal_osc32k, .parent = &xtal_osc32k,
}; };
static struct clk *onchip_clks[] = { static struct clk *onchip_clks[] = {

76
hw/timer/pxa2xx_timer.c
View file

@ -19,41 +19,41 @@
#include "qom/object.h" #include "qom/object.h"
#include "system/watchdog.h" #include "system/watchdog.h"
#define OSMR0 0x00 #define OSMR0 0x00
#define OSMR1 0x04 #define OSMR1 0x04
#define OSMR2 0x08 #define OSMR2 0x08
#define OSMR3 0x0c #define OSMR3 0x0c
#define OSMR4 0x80 #define OSMR4 0x80
#define OSMR5 0x84 #define OSMR5 0x84
#define OSMR6 0x88 #define OSMR6 0x88
#define OSMR7 0x8c #define OSMR7 0x8c
#define OSMR8 0x90 #define OSMR8 0x90
#define OSMR9 0x94 #define OSMR9 0x94
#define OSMR10 0x98 #define OSMR10 0x98
#define OSMR11 0x9c #define OSMR11 0x9c
#define OSCR 0x10 /* OS Timer Count */ #define OSCR 0x10 /* OS Timer Count */
#define OSCR4 0x40 #define OSCR4 0x40
#define OSCR5 0x44 #define OSCR5 0x44
#define OSCR6 0x48 #define OSCR6 0x48
#define OSCR7 0x4c #define OSCR7 0x4c
#define OSCR8 0x50 #define OSCR8 0x50
#define OSCR9 0x54 #define OSCR9 0x54
#define OSCR10 0x58 #define OSCR10 0x58
#define OSCR11 0x5c #define OSCR11 0x5c
#define OSSR 0x14 /* Timer status register */ #define OSSR 0x14 /* Timer status register */
#define OWER 0x18 #define OWER 0x18
#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */ #define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
#define OMCR4 0xc0 /* OS Match Control registers */ #define OMCR4 0xc0 /* OS Match Control registers */
#define OMCR5 0xc4 #define OMCR5 0xc4
#define OMCR6 0xc8 #define OMCR6 0xc8
#define OMCR7 0xcc #define OMCR7 0xcc
#define OMCR8 0xd0 #define OMCR8 0xd0
#define OMCR9 0xd4 #define OMCR9 0xd4
#define OMCR10 0xd8 #define OMCR10 0xd8
#define OMCR11 0xdc #define OMCR11 0xdc
#define OSNR 0x20 #define OSNR 0x20
#define PXA25X_FREQ 3686400 /* 3.6864 MHz */ #define PXA25X_FREQ 3686400 /* 3.6864 MHz */
static int pxa2xx_timer4_freq[8] = { static int pxa2xx_timer4_freq[8] = {
[0] = 0, [0] = 0,
@ -106,7 +106,7 @@ struct PXA2xxTimerInfo {
PXA2xxTimer4 tm4[8]; PXA2xxTimer4 tm4[8];
}; };
#define PXA2XX_TIMER_HAVE_TM4 0 #define PXA2XX_TIMER_HAVE_TM4 0
static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s) static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s)
{ {
@ -230,7 +230,7 @@ static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
NANOSECONDS_PER_SECOND); NANOSECONDS_PER_SECOND);
case OIER: case OIER:
return s->irq_enabled; return s->irq_enabled;
case OSSR: /* Status register */ case OSSR: /* Status register */
return s->events; return s->events;
case OWER: case OWER:
return s->reset3; return s->reset3;
@ -336,7 +336,7 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset,
case OIER: case OIER:
s->irq_enabled = value & 0xfff; s->irq_enabled = value & 0xfff;
break; break;
case OSSR: /* Status register */ case OSSR: /* Status register */
value &= s->events; value &= s->events;
s->events &= ~value; s->events &= ~value;
for (i = 0; i < 4; i ++, value >>= 1) for (i = 0; i < 4; i ++, value >>= 1)
@ -345,7 +345,7 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset,
if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value) if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
qemu_irq_lower(s->irq4); qemu_irq_lower(s->irq4);
break; break;
case OWER: /* XXX: Reset on OSMR3 match? */ case OWER: /* XXX: Reset on OSMR3 match? */
s->reset3 = value; s->reset3 = value;
break; break;
case OMCR7: tm ++; case OMCR7: tm ++;

11
include/exec/helper-head.h.inc
View file

@ -58,6 +58,17 @@
# define dh_ctype_tl target_ulong # define dh_ctype_tl target_ulong
#endif /* COMPILING_PER_TARGET */ #endif /* COMPILING_PER_TARGET */
#if __SIZEOF_POINTER__ == 4
# define dh_alias_vaddr i32
# define dh_typecode_vaddr dh_typecode_i32
#elif __SIZEOF_POINTER__ == 8
# define dh_alias_vaddr i64
# define dh_typecode_vaddr dh_typecode_i64
#else
# error "sizeof pointer is different from {4,8}"
#endif /* __SIZEOF_POINTER__ */
# define dh_ctype_vaddr uintptr_t
/* We can't use glue() here because it falls foul of C preprocessor /* We can't use glue() here because it falls foul of C preprocessor
recursive expansion rules. */ recursive expansion rules. */
#define dh_retvar_decl0_void void #define dh_retvar_decl0_void void

534
include/hw/arm/omap.h
View file

@ -25,24 +25,24 @@
#include "qemu/log.h" #include "qemu/log.h"
#include "qom/object.h" #include "qom/object.h"
# define OMAP_EMIFS_BASE 0x00000000 #define OMAP_EMIFS_BASE 0x00000000
# define OMAP_CS0_BASE 0x00000000 #define OMAP_CS0_BASE 0x00000000
# define OMAP_CS1_BASE 0x04000000 #define OMAP_CS1_BASE 0x04000000
# define OMAP_CS2_BASE 0x08000000 #define OMAP_CS2_BASE 0x08000000
# define OMAP_CS3_BASE 0x0c000000 #define OMAP_CS3_BASE 0x0c000000
# define OMAP_EMIFF_BASE 0x10000000 #define OMAP_EMIFF_BASE 0x10000000
# define OMAP_IMIF_BASE 0x20000000 #define OMAP_IMIF_BASE 0x20000000
# define OMAP_LOCALBUS_BASE 0x30000000 #define OMAP_LOCALBUS_BASE 0x30000000
# define OMAP_MPUI_BASE 0xe1000000 #define OMAP_MPUI_BASE 0xe1000000
# define OMAP730_SRAM_SIZE 0x00032000 #define OMAP730_SRAM_SIZE 0x00032000
# define OMAP15XX_SRAM_SIZE 0x00030000 #define OMAP15XX_SRAM_SIZE 0x00030000
# define OMAP16XX_SRAM_SIZE 0x00004000 #define OMAP16XX_SRAM_SIZE 0x00004000
# define OMAP1611_SRAM_SIZE 0x0003e800 #define OMAP1611_SRAM_SIZE 0x0003e800
# define OMAP_CS0_SIZE 0x04000000 #define OMAP_CS0_SIZE 0x04000000
# define OMAP_CS1_SIZE 0x04000000 #define OMAP_CS1_SIZE 0x04000000
# define OMAP_CS2_SIZE 0x04000000 #define OMAP_CS2_SIZE 0x04000000
# define OMAP_CS3_SIZE 0x04000000 #define OMAP_CS3_SIZE 0x04000000
/* omap_clk.c */ /* omap_clk.c */
struct omap_mpu_state_s; struct omap_mpu_state_s;
@ -103,228 +103,228 @@ void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk);
* Common IRQ numbers for level 1 interrupt handler * Common IRQ numbers for level 1 interrupt handler
* See /usr/include/asm-arm/arch-omap/irqs.h in Linux. * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
*/ */
# define OMAP_INT_CAMERA 1 #define OMAP_INT_CAMERA 1
# define OMAP_INT_FIQ 3 #define OMAP_INT_FIQ 3
# define OMAP_INT_RTDX 6 #define OMAP_INT_RTDX 6
# define OMAP_INT_DSP_MMU_ABORT 7 #define OMAP_INT_DSP_MMU_ABORT 7
# define OMAP_INT_HOST 8 #define OMAP_INT_HOST 8
# define OMAP_INT_ABORT 9 #define OMAP_INT_ABORT 9
# define OMAP_INT_BRIDGE_PRIV 13 #define OMAP_INT_BRIDGE_PRIV 13
# define OMAP_INT_GPIO_BANK1 14 #define OMAP_INT_GPIO_BANK1 14
# define OMAP_INT_UART3 15 #define OMAP_INT_UART3 15
# define OMAP_INT_TIMER3 16 #define OMAP_INT_TIMER3 16
# define OMAP_INT_DMA_CH0_6 19 #define OMAP_INT_DMA_CH0_6 19
# define OMAP_INT_DMA_CH1_7 20 #define OMAP_INT_DMA_CH1_7 20
# define OMAP_INT_DMA_CH2_8 21 #define OMAP_INT_DMA_CH2_8 21
# define OMAP_INT_DMA_CH3 22 #define OMAP_INT_DMA_CH3 22
# define OMAP_INT_DMA_CH4 23 #define OMAP_INT_DMA_CH4 23
# define OMAP_INT_DMA_CH5 24 #define OMAP_INT_DMA_CH5 24
# define OMAP_INT_DMA_LCD 25 #define OMAP_INT_DMA_LCD 25
# define OMAP_INT_TIMER1 26 #define OMAP_INT_TIMER1 26
# define OMAP_INT_WD_TIMER 27 #define OMAP_INT_WD_TIMER 27
# define OMAP_INT_BRIDGE_PUB 28 #define OMAP_INT_BRIDGE_PUB 28
# define OMAP_INT_TIMER2 30 #define OMAP_INT_TIMER2 30
# define OMAP_INT_LCD_CTRL 31 #define OMAP_INT_LCD_CTRL 31
/* /*
* Common OMAP-15xx IRQ numbers for level 1 interrupt handler * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
*/ */
# define OMAP_INT_15XX_IH2_IRQ 0 #define OMAP_INT_15XX_IH2_IRQ 0
# define OMAP_INT_15XX_LB_MMU 17 #define OMAP_INT_15XX_LB_MMU 17
# define OMAP_INT_15XX_LOCAL_BUS 29 #define OMAP_INT_15XX_LOCAL_BUS 29
/* /*
* OMAP-1510 specific IRQ numbers for level 1 interrupt handler * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
*/ */
# define OMAP_INT_1510_SPI_TX 4 #define OMAP_INT_1510_SPI_TX 4
# define OMAP_INT_1510_SPI_RX 5 #define OMAP_INT_1510_SPI_RX 5
# define OMAP_INT_1510_DSP_MAILBOX1 10 #define OMAP_INT_1510_DSP_MAILBOX1 10
# define OMAP_INT_1510_DSP_MAILBOX2 11 #define OMAP_INT_1510_DSP_MAILBOX2 11
/* /*
* OMAP-310 specific IRQ numbers for level 1 interrupt handler * OMAP-310 specific IRQ numbers for level 1 interrupt handler
*/ */
# define OMAP_INT_310_McBSP2_TX 4 #define OMAP_INT_310_McBSP2_TX 4
# define OMAP_INT_310_McBSP2_RX 5 #define OMAP_INT_310_McBSP2_RX 5
# define OMAP_INT_310_HSB_MAILBOX1 12 #define OMAP_INT_310_HSB_MAILBOX1 12
# define OMAP_INT_310_HSAB_MMU 18 #define OMAP_INT_310_HSAB_MMU 18
/* /*
* OMAP-1610 specific IRQ numbers for level 1 interrupt handler * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
*/ */
# define OMAP_INT_1610_IH2_IRQ 0 #define OMAP_INT_1610_IH2_IRQ 0
# define OMAP_INT_1610_IH2_FIQ 2 #define OMAP_INT_1610_IH2_FIQ 2
# define OMAP_INT_1610_McBSP2_TX 4 #define OMAP_INT_1610_McBSP2_TX 4
# define OMAP_INT_1610_McBSP2_RX 5 #define OMAP_INT_1610_McBSP2_RX 5
# define OMAP_INT_1610_DSP_MAILBOX1 10 #define OMAP_INT_1610_DSP_MAILBOX1 10
# define OMAP_INT_1610_DSP_MAILBOX2 11 #define OMAP_INT_1610_DSP_MAILBOX2 11
# define OMAP_INT_1610_LCD_LINE 12 #define OMAP_INT_1610_LCD_LINE 12
# define OMAP_INT_1610_GPTIMER1 17 #define OMAP_INT_1610_GPTIMER1 17
# define OMAP_INT_1610_GPTIMER2 18 #define OMAP_INT_1610_GPTIMER2 18
# define OMAP_INT_1610_SSR_FIFO_0 29 #define OMAP_INT_1610_SSR_FIFO_0 29
/* /*
* OMAP-730 specific IRQ numbers for level 1 interrupt handler * OMAP-730 specific IRQ numbers for level 1 interrupt handler
*/ */
# define OMAP_INT_730_IH2_FIQ 0 #define OMAP_INT_730_IH2_FIQ 0
# define OMAP_INT_730_IH2_IRQ 1 #define OMAP_INT_730_IH2_IRQ 1
# define OMAP_INT_730_USB_NON_ISO 2 #define OMAP_INT_730_USB_NON_ISO 2
# define OMAP_INT_730_USB_ISO 3 #define OMAP_INT_730_USB_ISO 3
# define OMAP_INT_730_ICR 4 #define OMAP_INT_730_ICR 4
# define OMAP_INT_730_EAC 5 #define OMAP_INT_730_EAC 5
# define OMAP_INT_730_GPIO_BANK1 6 #define OMAP_INT_730_GPIO_BANK1 6
# define OMAP_INT_730_GPIO_BANK2 7 #define OMAP_INT_730_GPIO_BANK2 7
# define OMAP_INT_730_GPIO_BANK3 8 #define OMAP_INT_730_GPIO_BANK3 8
# define OMAP_INT_730_McBSP2TX 10 #define OMAP_INT_730_McBSP2TX 10
# define OMAP_INT_730_McBSP2RX 11 #define OMAP_INT_730_McBSP2RX 11
# define OMAP_INT_730_McBSP2RX_OVF 12 #define OMAP_INT_730_McBSP2RX_OVF 12
# define OMAP_INT_730_LCD_LINE 14 #define OMAP_INT_730_LCD_LINE 14
# define OMAP_INT_730_GSM_PROTECT 15 #define OMAP_INT_730_GSM_PROTECT 15
# define OMAP_INT_730_TIMER3 16 #define OMAP_INT_730_TIMER3 16
# define OMAP_INT_730_GPIO_BANK5 17 #define OMAP_INT_730_GPIO_BANK5 17
# define OMAP_INT_730_GPIO_BANK6 18 #define OMAP_INT_730_GPIO_BANK6 18
# define OMAP_INT_730_SPGIO_WR 29 #define OMAP_INT_730_SPGIO_WR 29
/* /*
* Common IRQ numbers for level 2 interrupt handler * Common IRQ numbers for level 2 interrupt handler
*/ */
# define OMAP_INT_KEYBOARD 1 #define OMAP_INT_KEYBOARD 1
# define OMAP_INT_uWireTX 2 #define OMAP_INT_uWireTX 2
# define OMAP_INT_uWireRX 3 #define OMAP_INT_uWireRX 3
# define OMAP_INT_I2C 4 #define OMAP_INT_I2C 4
# define OMAP_INT_MPUIO 5 #define OMAP_INT_MPUIO 5
# define OMAP_INT_USB_HHC_1 6 #define OMAP_INT_USB_HHC_1 6
# define OMAP_INT_McBSP3TX 10 #define OMAP_INT_McBSP3TX 10
# define OMAP_INT_McBSP3RX 11 #define OMAP_INT_McBSP3RX 11
# define OMAP_INT_McBSP1TX 12 #define OMAP_INT_McBSP1TX 12
# define OMAP_INT_McBSP1RX 13 #define OMAP_INT_McBSP1RX 13
# define OMAP_INT_UART1 14 #define OMAP_INT_UART1 14
# define OMAP_INT_UART2 15 #define OMAP_INT_UART2 15
# define OMAP_INT_USB_W2FC 20 #define OMAP_INT_USB_W2FC 20
# define OMAP_INT_1WIRE 21 #define OMAP_INT_1WIRE 21
# define OMAP_INT_OS_TIMER 22 #define OMAP_INT_OS_TIMER 22
# define OMAP_INT_OQN 23 #define OMAP_INT_OQN 23
# define OMAP_INT_GAUGE_32K 24 #define OMAP_INT_GAUGE_32K 24
# define OMAP_INT_RTC_TIMER 25 #define OMAP_INT_RTC_TIMER 25
# define OMAP_INT_RTC_ALARM 26 #define OMAP_INT_RTC_ALARM 26
# define OMAP_INT_DSP_MMU 28 #define OMAP_INT_DSP_MMU 28
/* /*
* OMAP-1510 specific IRQ numbers for level 2 interrupt handler * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
*/ */
# define OMAP_INT_1510_BT_MCSI1TX 16 #define OMAP_INT_1510_BT_MCSI1TX 16
# define OMAP_INT_1510_BT_MCSI1RX 17 #define OMAP_INT_1510_BT_MCSI1RX 17
# define OMAP_INT_1510_SoSSI_MATCH 19 #define OMAP_INT_1510_SoSSI_MATCH 19
# define OMAP_INT_1510_MEM_STICK 27 #define OMAP_INT_1510_MEM_STICK 27
# define OMAP_INT_1510_COM_SPI_RO 31 #define OMAP_INT_1510_COM_SPI_RO 31
/* /*
* OMAP-310 specific IRQ numbers for level 2 interrupt handler * OMAP-310 specific IRQ numbers for level 2 interrupt handler
*/ */
# define OMAP_INT_310_FAC 0 #define OMAP_INT_310_FAC 0
# define OMAP_INT_310_USB_HHC_2 7 #define OMAP_INT_310_USB_HHC_2 7
# define OMAP_INT_310_MCSI1_FE 16 #define OMAP_INT_310_MCSI1_FE 16
# define OMAP_INT_310_MCSI2_FE 17 #define OMAP_INT_310_MCSI2_FE 17
# define OMAP_INT_310_USB_W2FC_ISO 29 #define OMAP_INT_310_USB_W2FC_ISO 29
# define OMAP_INT_310_USB_W2FC_NON_ISO 30 #define OMAP_INT_310_USB_W2FC_NON_ISO 30
# define OMAP_INT_310_McBSP2RX_OF 31 #define OMAP_INT_310_McBSP2RX_OF 31
/* /*
* OMAP-1610 specific IRQ numbers for level 2 interrupt handler * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
*/ */
# define OMAP_INT_1610_FAC 0 #define OMAP_INT_1610_FAC 0
# define OMAP_INT_1610_USB_HHC_2 7 #define OMAP_INT_1610_USB_HHC_2 7
# define OMAP_INT_1610_USB_OTG 8 #define OMAP_INT_1610_USB_OTG 8
# define OMAP_INT_1610_SoSSI 9 #define OMAP_INT_1610_SoSSI 9
# define OMAP_INT_1610_BT_MCSI1TX 16 #define OMAP_INT_1610_BT_MCSI1TX 16
# define OMAP_INT_1610_BT_MCSI1RX 17 #define OMAP_INT_1610_BT_MCSI1RX 17
# define OMAP_INT_1610_SoSSI_MATCH 19 #define OMAP_INT_1610_SoSSI_MATCH 19
# define OMAP_INT_1610_MEM_STICK 27 #define OMAP_INT_1610_MEM_STICK 27
# define OMAP_INT_1610_McBSP2RX_OF 31 #define OMAP_INT_1610_McBSP2RX_OF 31
# define OMAP_INT_1610_STI 32 #define OMAP_INT_1610_STI 32
# define OMAP_INT_1610_STI_WAKEUP 33 #define OMAP_INT_1610_STI_WAKEUP 33
# define OMAP_INT_1610_GPTIMER3 34 #define OMAP_INT_1610_GPTIMER3 34
# define OMAP_INT_1610_GPTIMER4 35 #define OMAP_INT_1610_GPTIMER4 35
# define OMAP_INT_1610_GPTIMER5 36 #define OMAP_INT_1610_GPTIMER5 36
# define OMAP_INT_1610_GPTIMER6 37 #define OMAP_INT_1610_GPTIMER6 37
# define OMAP_INT_1610_GPTIMER7 38 #define OMAP_INT_1610_GPTIMER7 38
# define OMAP_INT_1610_GPTIMER8 39 #define OMAP_INT_1610_GPTIMER8 39
# define OMAP_INT_1610_GPIO_BANK2 40 #define OMAP_INT_1610_GPIO_BANK2 40
# define OMAP_INT_1610_GPIO_BANK3 41 #define OMAP_INT_1610_GPIO_BANK3 41
# define OMAP_INT_1610_MMC2 42 #define OMAP_INT_1610_MMC2 42
# define OMAP_INT_1610_CF 43 #define OMAP_INT_1610_CF 43
# define OMAP_INT_1610_WAKE_UP_REQ 46 #define OMAP_INT_1610_WAKE_UP_REQ 46
# define OMAP_INT_1610_GPIO_BANK4 48 #define OMAP_INT_1610_GPIO_BANK4 48
# define OMAP_INT_1610_SPI 49 #define OMAP_INT_1610_SPI 49
# define OMAP_INT_1610_DMA_CH6 53 #define OMAP_INT_1610_DMA_CH6 53
# define OMAP_INT_1610_DMA_CH7 54 #define OMAP_INT_1610_DMA_CH7 54
# define OMAP_INT_1610_DMA_CH8 55 #define OMAP_INT_1610_DMA_CH8 55
# define OMAP_INT_1610_DMA_CH9 56 #define OMAP_INT_1610_DMA_CH9 56
# define OMAP_INT_1610_DMA_CH10 57 #define OMAP_INT_1610_DMA_CH10 57
# define OMAP_INT_1610_DMA_CH11 58 #define OMAP_INT_1610_DMA_CH11 58
# define OMAP_INT_1610_DMA_CH12 59 #define OMAP_INT_1610_DMA_CH12 59
# define OMAP_INT_1610_DMA_CH13 60 #define OMAP_INT_1610_DMA_CH13 60
# define OMAP_INT_1610_DMA_CH14 61 #define OMAP_INT_1610_DMA_CH14 61
# define OMAP_INT_1610_DMA_CH15 62 #define OMAP_INT_1610_DMA_CH15 62
# define OMAP_INT_1610_NAND 63 #define OMAP_INT_1610_NAND 63
/* /*
* OMAP-730 specific IRQ numbers for level 2 interrupt handler * OMAP-730 specific IRQ numbers for level 2 interrupt handler
*/ */
# define OMAP_INT_730_HW_ERRORS 0 #define OMAP_INT_730_HW_ERRORS 0
# define OMAP_INT_730_NFIQ_PWR_FAIL 1 #define OMAP_INT_730_NFIQ_PWR_FAIL 1
# define OMAP_INT_730_CFCD 2 #define OMAP_INT_730_CFCD 2
# define OMAP_INT_730_CFIREQ 3 #define OMAP_INT_730_CFIREQ 3
# define OMAP_INT_730_I2C 4 #define OMAP_INT_730_I2C 4
# define OMAP_INT_730_PCC 5 #define OMAP_INT_730_PCC 5
# define OMAP_INT_730_MPU_EXT_NIRQ 6 #define OMAP_INT_730_MPU_EXT_NIRQ 6
# define OMAP_INT_730_SPI_100K_1 7 #define OMAP_INT_730_SPI_100K_1 7
# define OMAP_INT_730_SYREN_SPI 8 #define OMAP_INT_730_SYREN_SPI 8
# define OMAP_INT_730_VLYNQ 9 #define OMAP_INT_730_VLYNQ 9
# define OMAP_INT_730_GPIO_BANK4 10 #define OMAP_INT_730_GPIO_BANK4 10
# define OMAP_INT_730_McBSP1TX 11 #define OMAP_INT_730_McBSP1TX 11
# define OMAP_INT_730_McBSP1RX 12 #define OMAP_INT_730_McBSP1RX 12
# define OMAP_INT_730_McBSP1RX_OF 13 #define OMAP_INT_730_McBSP1RX_OF 13
# define OMAP_INT_730_UART_MODEM_IRDA_2 14 #define OMAP_INT_730_UART_MODEM_IRDA_2 14
# define OMAP_INT_730_UART_MODEM_1 15 #define OMAP_INT_730_UART_MODEM_1 15
# define OMAP_INT_730_MCSI 16 #define OMAP_INT_730_MCSI 16
# define OMAP_INT_730_uWireTX 17 #define OMAP_INT_730_uWireTX 17
# define OMAP_INT_730_uWireRX 18 #define OMAP_INT_730_uWireRX 18
# define OMAP_INT_730_SMC_CD 19 #define OMAP_INT_730_SMC_CD 19
# define OMAP_INT_730_SMC_IREQ 20 #define OMAP_INT_730_SMC_IREQ 20
# define OMAP_INT_730_HDQ_1WIRE 21 #define OMAP_INT_730_HDQ_1WIRE 21
# define OMAP_INT_730_TIMER32K 22 #define OMAP_INT_730_TIMER32K 22
# define OMAP_INT_730_MMC_SDIO 23 #define OMAP_INT_730_MMC_SDIO 23
# define OMAP_INT_730_UPLD 24 #define OMAP_INT_730_UPLD 24
# define OMAP_INT_730_USB_HHC_1 27 #define OMAP_INT_730_USB_HHC_1 27
# define OMAP_INT_730_USB_HHC_2 28 #define OMAP_INT_730_USB_HHC_2 28
# define OMAP_INT_730_USB_GENI 29 #define OMAP_INT_730_USB_GENI 29
# define OMAP_INT_730_USB_OTG 30 #define OMAP_INT_730_USB_OTG 30
# define OMAP_INT_730_CAMERA_IF 31 #define OMAP_INT_730_CAMERA_IF 31
# define OMAP_INT_730_RNG 32 #define OMAP_INT_730_RNG 32
# define OMAP_INT_730_DUAL_MODE_TIMER 33 #define OMAP_INT_730_DUAL_MODE_TIMER 33
# define OMAP_INT_730_DBB_RF_EN 34 #define OMAP_INT_730_DBB_RF_EN 34
# define OMAP_INT_730_MPUIO_KEYPAD 35 #define OMAP_INT_730_MPUIO_KEYPAD 35
# define OMAP_INT_730_SHA1_MD5 36 #define OMAP_INT_730_SHA1_MD5 36
# define OMAP_INT_730_SPI_100K_2 37 #define OMAP_INT_730_SPI_100K_2 37
# define OMAP_INT_730_RNG_IDLE 38 #define OMAP_INT_730_RNG_IDLE 38
# define OMAP_INT_730_MPUIO 39 #define OMAP_INT_730_MPUIO 39
# define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 #define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
# define OMAP_INT_730_LLPC_OE_FALLING 41 #define OMAP_INT_730_LLPC_OE_FALLING 41
# define OMAP_INT_730_LLPC_OE_RISING 42 #define OMAP_INT_730_LLPC_OE_RISING 42
# define OMAP_INT_730_LLPC_VSYNC 43 #define OMAP_INT_730_LLPC_VSYNC 43
# define OMAP_INT_730_WAKE_UP_REQ 46 #define OMAP_INT_730_WAKE_UP_REQ 46
# define OMAP_INT_730_DMA_CH6 53 #define OMAP_INT_730_DMA_CH6 53
# define OMAP_INT_730_DMA_CH7 54 #define OMAP_INT_730_DMA_CH7 54
# define OMAP_INT_730_DMA_CH8 55 #define OMAP_INT_730_DMA_CH8 55
# define OMAP_INT_730_DMA_CH9 56 #define OMAP_INT_730_DMA_CH9 56
# define OMAP_INT_730_DMA_CH10 57 #define OMAP_INT_730_DMA_CH10 57
# define OMAP_INT_730_DMA_CH11 58 #define OMAP_INT_730_DMA_CH11 58
# define OMAP_INT_730_DMA_CH12 59 #define OMAP_INT_730_DMA_CH12 59
# define OMAP_INT_730_DMA_CH13 60 #define OMAP_INT_730_DMA_CH13 60
# define OMAP_INT_730_DMA_CH14 61 #define OMAP_INT_730_DMA_CH14 61
# define OMAP_INT_730_DMA_CH15 62 #define OMAP_INT_730_DMA_CH15 62
# define OMAP_INT_730_NAND 63 #define OMAP_INT_730_NAND 63
/* omap_dma.c */ /* omap_dma.c */
enum omap_dma_model { enum omap_dma_model {
@ -353,9 +353,9 @@ struct dma_irq_map {
enum omap_dma_port { enum omap_dma_port {
emiff = 0, emiff = 0,
emifs, emifs,
imif, /* omap16xx: ocp_t1 */ imif, /* omap16xx: ocp_t1 */
tipb, tipb,
local, /* omap16xx: ocp_t2 */ local, /* omap16xx: ocp_t2 */
tipb_mpui, tipb_mpui,
__omap_dma_port_last, __omap_dma_port_last,
}; };
@ -418,65 +418,65 @@ struct omap_dma_lcd_channel_s {
* DMA request numbers for OMAP1 * DMA request numbers for OMAP1
* See /usr/include/asm-arm/arch-omap/dma.h in Linux. * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
*/ */
# define OMAP_DMA_NO_DEVICE 0 #define OMAP_DMA_NO_DEVICE 0
# define OMAP_DMA_MCSI1_TX 1 #define OMAP_DMA_MCSI1_TX 1
# define OMAP_DMA_MCSI1_RX 2 #define OMAP_DMA_MCSI1_RX 2
# define OMAP_DMA_I2C_RX 3 #define OMAP_DMA_I2C_RX 3
# define OMAP_DMA_I2C_TX 4 #define OMAP_DMA_I2C_TX 4
# define OMAP_DMA_EXT_NDMA_REQ0 5 #define OMAP_DMA_EXT_NDMA_REQ0 5
# define OMAP_DMA_EXT_NDMA_REQ1 6 #define OMAP_DMA_EXT_NDMA_REQ1 6
# define OMAP_DMA_UWIRE_TX 7 #define OMAP_DMA_UWIRE_TX 7
# define OMAP_DMA_MCBSP1_TX 8 #define OMAP_DMA_MCBSP1_TX 8
# define OMAP_DMA_MCBSP1_RX 9 #define OMAP_DMA_MCBSP1_RX 9
# define OMAP_DMA_MCBSP3_TX 10 #define OMAP_DMA_MCBSP3_TX 10
# define OMAP_DMA_MCBSP3_RX 11 #define OMAP_DMA_MCBSP3_RX 11
# define OMAP_DMA_UART1_TX 12 #define OMAP_DMA_UART1_TX 12
# define OMAP_DMA_UART1_RX 13 #define OMAP_DMA_UART1_RX 13
# define OMAP_DMA_UART2_TX 14 #define OMAP_DMA_UART2_TX 14
# define OMAP_DMA_UART2_RX 15 #define OMAP_DMA_UART2_RX 15
# define OMAP_DMA_MCBSP2_TX 16 #define OMAP_DMA_MCBSP2_TX 16
# define OMAP_DMA_MCBSP2_RX 17 #define OMAP_DMA_MCBSP2_RX 17
# define OMAP_DMA_UART3_TX 18 #define OMAP_DMA_UART3_TX 18
# define OMAP_DMA_UART3_RX 19 #define OMAP_DMA_UART3_RX 19
# define OMAP_DMA_CAMERA_IF_RX 20 #define OMAP_DMA_CAMERA_IF_RX 20
# define OMAP_DMA_MMC_TX 21 #define OMAP_DMA_MMC_TX 21
# define OMAP_DMA_MMC_RX 22 #define OMAP_DMA_MMC_RX 22
# define OMAP_DMA_NAND 23 /* Not in OMAP310 */ #define OMAP_DMA_NAND 23 /* Not in OMAP310 */
# define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ #define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */
# define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ #define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */
# define OMAP_DMA_USB_W2FC_RX0 26 #define OMAP_DMA_USB_W2FC_RX0 26
# define OMAP_DMA_USB_W2FC_RX1 27 #define OMAP_DMA_USB_W2FC_RX1 27
# define OMAP_DMA_USB_W2FC_RX2 28 #define OMAP_DMA_USB_W2FC_RX2 28
# define OMAP_DMA_USB_W2FC_TX0 29 #define OMAP_DMA_USB_W2FC_TX0 29
# define OMAP_DMA_USB_W2FC_TX1 30 #define OMAP_DMA_USB_W2FC_TX1 30
# define OMAP_DMA_USB_W2FC_TX2 31 #define OMAP_DMA_USB_W2FC_TX2 31
/* These are only for 1610 */ /* These are only for 1610 */
# define OMAP_DMA_CRYPTO_DES_IN 32 #define OMAP_DMA_CRYPTO_DES_IN 32
# define OMAP_DMA_SPI_TX 33 #define OMAP_DMA_SPI_TX 33
# define OMAP_DMA_SPI_RX 34 #define OMAP_DMA_SPI_RX 34
# define OMAP_DMA_CRYPTO_HASH 35 #define OMAP_DMA_CRYPTO_HASH 35
# define OMAP_DMA_CCP_ATTN 36 #define OMAP_DMA_CCP_ATTN 36
# define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 #define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
# define OMAP_DMA_CMT_APE_TX_CHAN_0 38 #define OMAP_DMA_CMT_APE_TX_CHAN_0 38
# define OMAP_DMA_CMT_APE_RV_CHAN_0 39 #define OMAP_DMA_CMT_APE_RV_CHAN_0 39
# define OMAP_DMA_CMT_APE_TX_CHAN_1 40 #define OMAP_DMA_CMT_APE_TX_CHAN_1 40
# define OMAP_DMA_CMT_APE_RV_CHAN_1 41 #define OMAP_DMA_CMT_APE_RV_CHAN_1 41
# define OMAP_DMA_CMT_APE_TX_CHAN_2 42 #define OMAP_DMA_CMT_APE_TX_CHAN_2 42
# define OMAP_DMA_CMT_APE_RV_CHAN_2 43 #define OMAP_DMA_CMT_APE_RV_CHAN_2 43
# define OMAP_DMA_CMT_APE_TX_CHAN_3 44 #define OMAP_DMA_CMT_APE_TX_CHAN_3 44
# define OMAP_DMA_CMT_APE_RV_CHAN_3 45 #define OMAP_DMA_CMT_APE_RV_CHAN_3 45
# define OMAP_DMA_CMT_APE_TX_CHAN_4 46 #define OMAP_DMA_CMT_APE_TX_CHAN_4 46
# define OMAP_DMA_CMT_APE_RV_CHAN_4 47 #define OMAP_DMA_CMT_APE_RV_CHAN_4 47
# define OMAP_DMA_CMT_APE_TX_CHAN_5 48 #define OMAP_DMA_CMT_APE_TX_CHAN_5 48
# define OMAP_DMA_CMT_APE_RV_CHAN_5 49 #define OMAP_DMA_CMT_APE_RV_CHAN_5 49
# define OMAP_DMA_CMT_APE_TX_CHAN_6 50 #define OMAP_DMA_CMT_APE_TX_CHAN_6 50
# define OMAP_DMA_CMT_APE_RV_CHAN_6 51 #define OMAP_DMA_CMT_APE_RV_CHAN_6 51
# define OMAP_DMA_CMT_APE_TX_CHAN_7 52 #define OMAP_DMA_CMT_APE_TX_CHAN_7 52
# define OMAP_DMA_CMT_APE_RV_CHAN_7 53 #define OMAP_DMA_CMT_APE_RV_CHAN_7 53
# define OMAP_DMA_MMC2_TX 54 #define OMAP_DMA_MMC2_TX 54
# define OMAP_DMA_MMC2_RX 55 #define OMAP_DMA_MMC2_RX 55
# define OMAP_DMA_CRYPTO_DES_OUT 56 #define OMAP_DMA_CRYPTO_DES_OUT 56
struct omap_uart_s; struct omap_uart_s;
struct omap_uart_s *omap_uart_init(hwaddr base, struct omap_uart_s *omap_uart_init(hwaddr base,
@ -542,14 +542,14 @@ void omap_mmc_set_clk(DeviceState *dev, omap_clk clk);
/* omap_i2c.c */ /* omap_i2c.c */
I2CBus *omap_i2c_bus(DeviceState *omap_i2c); I2CBus *omap_i2c_bus(DeviceState *omap_i2c);
# define cpu_is_omap310(cpu) (cpu->mpu_model == omap310) #define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
# define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510) #define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
# define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610) #define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
# define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710) #define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
# define cpu_is_omap15xx(cpu) \ #define cpu_is_omap15xx(cpu) \
(cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
# define cpu_is_omap16xx(cpu) \ #define cpu_is_omap16xx(cpu) \
(cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
struct omap_mpu_state_s { struct omap_mpu_state_s {
@ -685,14 +685,14 @@ void omap_badwidth_write32(void *opaque, hwaddr addr,
void omap_mpu_wakeup(void *opaque, int irq, int req); void omap_mpu_wakeup(void *opaque, int irq, int req);
# define OMAP_BAD_REG(paddr) \ #define OMAP_BAD_REG(paddr) \
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \
__func__, paddr) __func__, paddr)
# define OMAP_RO_REG(paddr) \ #define OMAP_RO_REG(paddr) \
qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \ qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \
HWADDR_PRIx "\n", \ HWADDR_PRIx "\n", \
__func__, paddr) __func__, paddr)
# define OMAP_MPUI_REG_MASK 0x000007ff #define OMAP_MPUI_REG_MASK 0x000007ff
#endif #endif

2
include/hw/arm/sharpsl.h
View file

@ -11,7 +11,7 @@
/* zaurus.c */ /* zaurus.c */
#define SL_PXA_PARAM_BASE 0xa0000a00 #define SL_PXA_PARAM_BASE 0xa0000a00
void sl_bootparam_write(hwaddr ptr); void sl_bootparam_write(hwaddr ptr);
#endif #endif

4
include/hw/arm/soc_dma.h
View file

@ -54,7 +54,7 @@ struct soc_dma_ch_s {
int bytes; int bytes;
/* Initialised by the DMA module, call soc_dma_ch_update after writing. */ /* Initialised by the DMA module, call soc_dma_ch_update after writing. */
enum soc_dma_access_type type[2]; enum soc_dma_access_type type[2];
hwaddr vaddr[2]; /* Updated by .transfer_fn(). */ hwaddr vaddr[2]; /* Updated by .transfer_fn(). */
/* Private */ /* Private */
void *paddr[2]; void *paddr[2];
soc_dma_io_t io_fn[2]; soc_dma_io_t io_fn[2];
@ -70,7 +70,7 @@ struct soc_dma_ch_s {
struct soc_dma_s { struct soc_dma_s {
/* Following fields are set by the SoC DMA module and can be used /* Following fields are set by the SoC DMA module and can be used
* by anybody. */ * by anybody. */
uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */ uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */
qemu_irq *drq; qemu_irq *drq;
void *opaque; void *opaque;
int64_t freq; int64_t freq;

1
include/system/hvf.h
View file

@ -17,6 +17,7 @@
#include "qemu/queue.h" #include "qemu/queue.h"
#include "exec/vaddr.h" #include "exec/vaddr.h"
#include "qom/object.h" #include "qom/object.h"
#include "exec/vaddr.h"
#ifdef COMPILING_PER_TARGET #ifdef COMPILING_PER_TARGET
# ifdef CONFIG_HVF # ifdef CONFIG_HVF

1
include/tcg/tcg-op-common.h
View file

@ -14,6 +14,7 @@
TCGv_i32 tcg_constant_i32(int32_t val); TCGv_i32 tcg_constant_i32(int32_t val);
TCGv_i64 tcg_constant_i64(int64_t val); TCGv_i64 tcg_constant_i64(int64_t val);
TCGv_vaddr tcg_constant_vaddr(uintptr_t val);
TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val);
TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val); TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val);

14
include/tcg/tcg.h
View file

@ -189,6 +189,7 @@ typedef tcg_target_ulong TCGArg;
* TCGv_i64 : 64 bit integer type * TCGv_i64 : 64 bit integer type
* TCGv_i128 : 128 bit integer type * TCGv_i128 : 128 bit integer type
* TCGv_ptr : a host pointer type * TCGv_ptr : a host pointer type
* TCGv_vaddr: an integer type wide enough to hold a target pointer type
* TCGv_vec : a host vector type; the exact size is not exposed * TCGv_vec : a host vector type; the exact size is not exposed
to the CPU front-end code. to the CPU front-end code.
* TCGv : an integer type the same size as target_ulong * TCGv : an integer type the same size as target_ulong
@ -217,6 +218,14 @@ typedef struct TCGv_ptr_d *TCGv_ptr;
typedef struct TCGv_vec_d *TCGv_vec; typedef struct TCGv_vec_d *TCGv_vec;
typedef TCGv_ptr TCGv_env; typedef TCGv_ptr TCGv_env;
#if __SIZEOF_POINTER__ == 4
typedef TCGv_i32 TCGv_vaddr;
#elif __SIZEOF_POINTER__ == 8
typedef TCGv_i64 TCGv_vaddr;
#else
# error "sizeof pointer is different from {4,8}"
#endif /* __SIZEOF_POINTER__ */
/* call flags */ /* call flags */
/* Helper does not read globals (either directly or through an exception). It /* Helper does not read globals (either directly or through an exception). It
implies TCG_CALL_NO_WRITE_GLOBALS. */ implies TCG_CALL_NO_WRITE_GLOBALS. */
@ -577,6 +586,11 @@ static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t)
return (TCGv_ptr)temp_tcgv_i32(t); return (TCGv_ptr)temp_tcgv_i32(t);
} }
static inline TCGv_vaddr temp_tcgv_vaddr(TCGTemp *t)
{
return (TCGv_vaddr)temp_tcgv_i32(t);
}
static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) static inline TCGv_vec temp_tcgv_vec(TCGTemp *t)
{ {
return (TCGv_vec)temp_tcgv_i32(t); return (TCGv_vec)temp_tcgv_i32(t);

78
meson.build
View file

@ -3709,6 +3709,8 @@ target_arch = {}
target_system_arch = {} target_system_arch = {}
target_user_arch = {} target_user_arch = {}
hw_common_arch = {} hw_common_arch = {}
target_common_arch = {}
target_common_system_arch = {}
# NOTE: the trace/ subdirectory needs the qapi_trace_events variable # NOTE: the trace/ subdirectory needs the qapi_trace_events variable
# that is filled in by qapi/. # that is filled in by qapi/.
@ -4107,29 +4109,59 @@ common_all = static_library('common',
# construct common libraries per base architecture # construct common libraries per base architecture
hw_common_arch_libs = {} hw_common_arch_libs = {}
target_common_arch_libs = {}
target_common_system_arch_libs = {}
foreach target : target_dirs foreach target : target_dirs
config_target = config_target_mak[target] config_target = config_target_mak[target]
target_base_arch = config_target['TARGET_BASE_ARCH'] target_base_arch = config_target['TARGET_BASE_ARCH']
target_inc = [include_directories('target' / target_base_arch)]
inc = [common_user_inc + target_inc]
# check if already generated # prevent common code to access cpu compile time definition,
if target_base_arch in hw_common_arch_libs # but still allow access to cpu.h
continue target_c_args = ['-DCPU_DEFS_H']
endif target_system_c_args = target_c_args + ['-DCOMPILING_SYSTEM_VS_USER', '-DCONFIG_SOFTMMU']
if target_base_arch in hw_common_arch if target_base_arch in hw_common_arch
target_inc = [include_directories('target' / target_base_arch)] if target_base_arch not in hw_common_arch_libs
src = hw_common_arch[target_base_arch] src = hw_common_arch[target_base_arch]
lib = static_library( lib = static_library(
'hw_' + target_base_arch, 'hw_' + target_base_arch,
build_by_default: false, build_by_default: false,
sources: src.all_sources() + genh, sources: src.all_sources() + genh,
include_directories: common_user_inc + target_inc, include_directories: inc,
implicit_include_directories: false, c_args: target_system_c_args,
# prevent common code to access cpu compile time dependencies: src.all_dependencies())
# definition, but still allow access to cpu.h hw_common_arch_libs += {target_base_arch: lib}
c_args: ['-DCPU_DEFS_H', '-DCOMPILING_SYSTEM_VS_USER', '-DCONFIG_SOFTMMU'], endif
dependencies: src.all_dependencies()) endif
hw_common_arch_libs += {target_base_arch: lib}
if target_base_arch in target_common_arch
if target_base_arch not in target_common_arch_libs
src = target_common_arch[target_base_arch]
lib = static_library(
'target_' + target_base_arch,
build_by_default: false,
sources: src.all_sources() + genh,
include_directories: inc,
c_args: target_c_args,
dependencies: src.all_dependencies())
target_common_arch_libs += {target_base_arch: lib}
endif
endif
if target_base_arch in target_common_system_arch
if target_base_arch not in target_common_system_arch_libs
src = target_common_system_arch[target_base_arch]
lib = static_library(
'target_system_' + target_base_arch,
build_by_default: false,
sources: src.all_sources() + genh,
include_directories: inc,
c_args: target_system_c_args,
dependencies: src.all_dependencies())
target_common_system_arch_libs += {target_base_arch: lib}
endif
endif endif
endforeach endforeach
@ -4300,12 +4332,24 @@ foreach target : target_dirs
target_common = common_ss.apply(config_target, strict: false) target_common = common_ss.apply(config_target, strict: false)
objects = [common_all.extract_objects(target_common.sources())] objects = [common_all.extract_objects(target_common.sources())]
arch_deps += target_common.dependencies() arch_deps += target_common.dependencies()
if target_base_arch in target_common_arch_libs
src = target_common_arch[target_base_arch].apply(config_target, strict: false)
lib = target_common_arch_libs[target_base_arch]
objects += lib.extract_objects(src.sources())
arch_deps += src.dependencies()
endif
if target_type == 'system' and target_base_arch in hw_common_arch_libs if target_type == 'system' and target_base_arch in hw_common_arch_libs
src = hw_common_arch[target_base_arch].apply(config_target, strict: false) src = hw_common_arch[target_base_arch].apply(config_target, strict: false)
lib = hw_common_arch_libs[target_base_arch] lib = hw_common_arch_libs[target_base_arch]
objects += lib.extract_objects(src.sources()) objects += lib.extract_objects(src.sources())
arch_deps += src.dependencies() arch_deps += src.dependencies()
endif endif
if target_type == 'system' and target_base_arch in target_common_system_arch_libs
src = target_common_system_arch[target_base_arch].apply(config_target, strict: false)
lib = target_common_system_arch_libs[target_base_arch]
objects += lib.extract_objects(src.sources())
arch_deps += src.dependencies()
endif
target_specific = specific_ss.apply(config_target, strict: false) target_specific = specific_ss.apply(config_target, strict: false)
arch_srcs += target_specific.sources() arch_srcs += target_specific.sources()

261
rust/hw/char/pl011/src/registers.rs
View file

@ -5,13 +5,13 @@
//! Device registers exposed as typed structs which are backed by arbitrary //! Device registers exposed as typed structs which are backed by arbitrary
//! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc. //! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc.
// For more detail see the PL011 Technical Reference Manual DDI0183:
// https://developer.arm.com/documentation/ddi0183/latest/
use bilge::prelude::*; use bilge::prelude::*;
use qemu_api::impl_vmstate_bitsized; use qemu_api::impl_vmstate_bitsized;
/// Offset of each register from the base memory address of the device. /// Offset of each register from the base memory address of the device.
///
/// # Source
/// ARM DDI 0183G, Table 3-1 p.3-3
#[doc(alias = "offset")] #[doc(alias = "offset")]
#[allow(non_camel_case_types)] #[allow(non_camel_case_types)]
#[repr(u64)] #[repr(u64)]
@ -87,48 +87,11 @@ pub struct Errors {
_reserved_unpredictable: u4, _reserved_unpredictable: u4,
} }
// TODO: FIFO Mode has different semantics
/// Data Register, `UARTDR` /// Data Register, `UARTDR`
/// ///
/// The `UARTDR` register is the data register. /// The `UARTDR` register is the data register; write for TX and
/// /// read for RX. It is a 12-bit register, where bits 7..0 are the
/// For words to be transmitted: /// character and bits 11..8 are error bits.
///
/// - if the FIFOs are enabled, data written to this location is pushed onto the
/// transmit
/// FIFO
/// - if the FIFOs are not enabled, data is stored in the transmitter holding
/// register (the
/// bottom word of the transmit FIFO).
///
/// The write operation initiates transmission from the UART. The data is
/// prefixed with a start bit, appended with the appropriate parity bit
/// (if parity is enabled), and a stop bit. The resultant word is then
/// transmitted.
///
/// For received words:
///
/// - if the FIFOs are enabled, the data byte and the 4-bit status (break,
/// frame, parity,
/// and overrun) is pushed onto the 12-bit wide receive FIFO
/// - if the FIFOs are not enabled, the data byte and status are stored in the
/// receiving
/// holding register (the bottom word of the receive FIFO).
///
/// The received data byte is read by performing reads from the `UARTDR`
/// register along with the corresponding status information. The status
/// information can also be read by a read of the `UARTRSR/UARTECR`
/// register.
///
/// # Note
///
/// You must disable the UART before any of the control registers are
/// reprogrammed. When the UART is disabled in the middle of
/// transmission or reception, it completes the current character before
/// stopping.
///
/// # Source
/// ARM DDI 0183G 3.3.1 Data Register, UARTDR
#[bitsize(32)] #[bitsize(32)]
#[derive(Clone, Copy, Default, DebugBits, FromBits)] #[derive(Clone, Copy, Default, DebugBits, FromBits)]
#[doc(alias = "UARTDR")] #[doc(alias = "UARTDR")]
@ -144,30 +107,17 @@ impl Data {
pub const BREAK: Self = Self { value: 1 << 10 }; pub const BREAK: Self = Self { value: 1 << 10 };
} }
// TODO: FIFO Mode has different semantics
/// Receive Status Register / Error Clear Register, `UARTRSR/UARTECR` /// Receive Status Register / Error Clear Register, `UARTRSR/UARTECR`
/// ///
/// The UARTRSR/UARTECR register is the receive status register/error clear /// This register provides a different way to read the four receive
/// register. Receive status can also be read from the `UARTRSR` /// status error bits that can be found in bits 11..8 of the UARTDR
/// register. If the status is read from this register, then the status /// on a read. It gets updated when the guest reads UARTDR, and the
/// information for break, framing and parity corresponds to the /// status bits correspond to that character that was just read.
/// data character read from the [Data register](Data), `UARTDR` prior to
/// reading the UARTRSR register. The status information for overrun is
/// set immediately when an overrun condition occurs.
/// ///
/// /// The TRM confusingly describes this offset as UARTRSR for reads
/// # Note /// and UARTECR for writes, but really it's a single error status
/// The received data character must be read first from the [Data /// register where writing anything to the register clears the error
/// Register](Data), `UARTDR` before reading the error status associated /// bits.
/// with that data character from the `UARTRSR` register. This read
/// sequence cannot be reversed, because the `UARTRSR` register is
/// updated only when a read occurs from the `UARTDR` register. However,
/// the status information can also be obtained by reading the `UARTDR`
/// register
///
/// # Source
/// ARM DDI 0183G 3.3.2 Receive Status Register/Error Clear Register,
/// UARTRSR/UARTECR
#[bitsize(32)] #[bitsize(32)]
#[derive(Clone, Copy, DebugBits, FromBits)] #[derive(Clone, Copy, DebugBits, FromBits)]
pub struct ReceiveStatusErrorClear { pub struct ReceiveStatusErrorClear {
@ -196,54 +146,29 @@ impl Default for ReceiveStatusErrorClear {
#[bitsize(32)] #[bitsize(32)]
#[derive(Clone, Copy, DebugBits, FromBits)] #[derive(Clone, Copy, DebugBits, FromBits)]
/// Flag Register, `UARTFR` /// Flag Register, `UARTFR`
///
/// This has the usual inbound RS232 modem-control signals, plus flags
/// for RX and TX FIFO fill levels and a BUSY flag.
#[doc(alias = "UARTFR")] #[doc(alias = "UARTFR")]
pub struct Flags { pub struct Flags {
/// CTS Clear to send. This bit is the complement of the UART clear to /// CTS: Clear to send
/// send, `nUARTCTS`, modem status input. That is, the bit is 1
/// when `nUARTCTS` is LOW.
pub clear_to_send: bool, pub clear_to_send: bool,
/// DSR Data set ready. This bit is the complement of the UART data set /// DSR: Data set ready
/// ready, `nUARTDSR`, modem status input. That is, the bit is 1 when
/// `nUARTDSR` is LOW.
pub data_set_ready: bool, pub data_set_ready: bool,
/// DCD Data carrier detect. This bit is the complement of the UART data /// DCD: Data carrier detect
/// carrier detect, `nUARTDCD`, modem status input. That is, the bit is
/// 1 when `nUARTDCD` is LOW.
pub data_carrier_detect: bool, pub data_carrier_detect: bool,
/// BUSY UART busy. If this bit is set to 1, the UART is busy /// BUSY: UART busy. In real hardware, set while the UART is
/// transmitting data. This bit remains set until the complete /// busy transmitting data. QEMU's implementation never sets BUSY.
/// byte, including all the stop bits, has been sent from the
/// shift register. This bit is set as soon as the transmit FIFO
/// becomes non-empty, regardless of whether the UART is enabled
/// or not.
pub busy: bool, pub busy: bool,
/// RXFE Receive FIFO empty. The meaning of this bit depends on the /// RXFE: Receive FIFO empty
/// state of the FEN bit in the UARTLCR_H register. If the FIFO
/// is disabled, this bit is set when the receive holding
/// register is empty. If the FIFO is enabled, the RXFE bit is
/// set when the receive FIFO is empty.
pub receive_fifo_empty: bool, pub receive_fifo_empty: bool,
/// TXFF Transmit FIFO full. The meaning of this bit depends on the /// TXFF: Transmit FIFO full
/// state of the FEN bit in the UARTLCR_H register. If the FIFO
/// is disabled, this bit is set when the transmit holding
/// register is full. If the FIFO is enabled, the TXFF bit is
/// set when the transmit FIFO is full.
pub transmit_fifo_full: bool, pub transmit_fifo_full: bool,
/// RXFF Receive FIFO full. The meaning of this bit depends on the state /// RXFF: Receive FIFO full
/// of the FEN bit in the UARTLCR_H register. If the FIFO is
/// disabled, this bit is set when the receive holding register
/// is full. If the FIFO is enabled, the RXFF bit is set when
/// the receive FIFO is full.
pub receive_fifo_full: bool, pub receive_fifo_full: bool,
/// Transmit FIFO empty. The meaning of this bit depends on the state of /// TXFE: Transmit FIFO empty
/// the FEN bit in the [Line Control register](LineControl),
/// `UARTLCR_H`. If the FIFO is disabled, this bit is set when the
/// transmit holding register is empty. If the FIFO is enabled,
/// the TXFE bit is set when the transmit FIFO is empty. This
/// bit does not indicate if there is data in the transmit shift
/// register.
pub transmit_fifo_empty: bool, pub transmit_fifo_empty: bool,
/// `RI`, is `true` when `nUARTRI` is `LOW`. /// RI: Ring indicator
pub ring_indicator: bool, pub ring_indicator: bool,
_reserved_zero_no_modify: u23, _reserved_zero_no_modify: u23,
} }
@ -270,54 +195,23 @@ impl Default for Flags {
/// Line Control Register, `UARTLCR_H` /// Line Control Register, `UARTLCR_H`
#[doc(alias = "UARTLCR_H")] #[doc(alias = "UARTLCR_H")]
pub struct LineControl { pub struct LineControl {
/// BRK Send break. /// BRK: Send break
///
/// If this bit is set to `1`, a low-level is continually output on the
/// `UARTTXD` output, after completing transmission of the
/// current character. For the proper execution of the break command,
/// the software must set this bit for at least two complete
/// frames. For normal use, this bit must be cleared to `0`.
pub send_break: bool, pub send_break: bool,
/// 1 PEN Parity enable: /// PEN: Parity enable
///
/// - 0 = parity is disabled and no parity bit added to the data frame
/// - 1 = parity checking and generation is enabled.
///
/// See Table 3-11 on page 3-14 for the parity truth table.
pub parity_enabled: bool, pub parity_enabled: bool,
/// EPS Even parity select. Controls the type of parity the UART uses /// EPS: Even parity select
/// during transmission and reception:
/// - 0 = odd parity. The UART generates or checks for an odd number of 1s
/// in the data and parity bits.
/// - 1 = even parity. The UART generates or checks for an even number of 1s
/// in the data and parity bits.
/// This bit has no effect when the `PEN` bit disables parity checking
/// and generation. See Table 3-11 on page 3-14 for the parity
/// truth table.
pub parity: Parity, pub parity: Parity,
/// 3 STP2 Two stop bits select. If this bit is set to 1, two stop bits /// STP2: Two stop bits select
/// are transmitted at the end of the frame. The receive
/// logic does not check for two stop bits being received.
pub two_stops_bits: bool, pub two_stops_bits: bool,
/// FEN Enable FIFOs: /// FEN: Enable FIFOs
/// 0 = FIFOs are disabled (character mode) that is, the FIFOs become
/// 1-byte-deep holding registers 1 = transmit and receive FIFO
/// buffers are enabled (FIFO mode).
pub fifos_enabled: Mode, pub fifos_enabled: Mode,
/// WLEN Word length. These bits indicate the number of data bits /// WLEN: Word length in bits
/// transmitted or received in a frame as follows: b11 = 8 bits /// b11 = 8 bits
/// b10 = 7 bits /// b10 = 7 bits
/// b01 = 6 bits /// b01 = 6 bits
/// b00 = 5 bits. /// b00 = 5 bits.
pub word_length: WordLength, pub word_length: WordLength,
/// 7 SPS Stick parity select. /// SPS Stick parity select
/// 0 = stick parity is disabled
/// 1 = either:
/// • if the EPS bit is 0 then the parity bit is transmitted and checked
/// as a 1 • if the EPS bit is 1 then the parity bit is
/// transmitted and checked as a 0. This bit has no effect when
/// the PEN bit disables parity checking and generation. See Table 3-11
/// on page 3-14 for the parity truth table.
pub sticky_parity: bool, pub sticky_parity: bool,
/// 31:8 - Reserved, do not modify, read as zero. /// 31:8 - Reserved, do not modify, read as zero.
_reserved_zero_no_modify: u24, _reserved_zero_no_modify: u24,
@ -342,11 +236,7 @@ impl Default for LineControl {
/// `EPS` "Even parity select", field of [Line Control /// `EPS` "Even parity select", field of [Line Control
/// register](LineControl). /// register](LineControl).
pub enum Parity { pub enum Parity {
/// - 0 = odd parity. The UART generates or checks for an odd number of 1s
/// in the data and parity bits.
Odd = 0, Odd = 0,
/// - 1 = even parity. The UART generates or checks for an even number of 1s
/// in the data and parity bits.
Even = 1, Even = 1,
} }
@ -381,88 +271,39 @@ pub enum WordLength {
/// Control Register, `UARTCR` /// Control Register, `UARTCR`
/// ///
/// The `UARTCR` register is the control register. All the bits are cleared /// The `UARTCR` register is the control register. It contains various
/// to `0` on reset except for bits `9` and `8` that are set to `1`. /// enable bits, and the bits to write to set the usual outbound RS232
/// /// modem control signals. All bits reset to 0 except TXE and RXE.
/// # Source
/// ARM DDI 0183G, 3.3.8 Control Register, `UARTCR`, Table 3-12
#[bitsize(32)] #[bitsize(32)]
#[doc(alias = "UARTCR")] #[doc(alias = "UARTCR")]
#[derive(Clone, Copy, DebugBits, FromBits)] #[derive(Clone, Copy, DebugBits, FromBits)]
pub struct Control { pub struct Control {
/// `UARTEN` UART enable: 0 = UART is disabled. If the UART is disabled /// `UARTEN` UART enable: 0 = UART is disabled.
/// in the middle of transmission or reception, it completes the current
/// character before stopping. 1 = the UART is enabled. Data
/// transmission and reception occurs for either UART signals or SIR
/// signals depending on the setting of the SIREN bit.
pub enable_uart: bool, pub enable_uart: bool,
/// `SIREN` `SIR` enable: 0 = IrDA SIR ENDEC is disabled. `nSIROUT` /// `SIREN` `SIR` enable: disable or enable IrDA SIR ENDEC.
/// remains LOW (no light pulse generated), and signal transitions on /// QEMU does not model this.
/// SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is
/// transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH,
/// in the marking state. Signal transitions on UARTRXD or modem status
/// inputs have no effect. This bit has no effect if the UARTEN bit
/// disables the UART.
pub enable_sir: bool, pub enable_sir: bool,
/// `SIRLP` SIR low-power IrDA mode. This bit selects the IrDA encoding /// `SIRLP` SIR low-power IrDA mode. QEMU does not model this.
/// mode. If this bit is cleared to 0, low-level bits are transmitted as
/// an active high pulse with a width of 3/ 16th of the bit period. If
/// this bit is set to 1, low-level bits are transmitted with a pulse
/// width that is 3 times the period of the IrLPBaud16 input signal,
/// regardless of the selected bit rate. Setting this bit uses less
/// power, but might reduce transmission distances.
pub sir_lowpower_irda_mode: u1, pub sir_lowpower_irda_mode: u1,
/// Reserved, do not modify, read as zero. /// Reserved, do not modify, read as zero.
_reserved_zero_no_modify: u4, _reserved_zero_no_modify: u4,
/// `LBE` Loopback enable. If this bit is set to 1 and the SIREN bit is /// `LBE` Loopback enable: feed UART output back to the input
/// set to 1 and the SIRTEST bit in the Test Control register, UARTTCR
/// on page 4-5 is set to 1, then the nSIROUT path is inverted, and fed
/// through to the SIRIN path. The SIRTEST bit in the test register must
/// be set to 1 to override the normal half-duplex SIR operation. This
/// must be the requirement for accessing the test registers during
/// normal operation, and SIRTEST must be cleared to 0 when loopback
/// testing is finished. This feature reduces the amount of external
/// coupling required during system test. If this bit is set to 1, and
/// the SIRTEST bit is set to 0, the UARTTXD path is fed through to the
/// UARTRXD path. In either SIR mode or UART mode, when this bit is set,
/// the modem outputs are also fed through to the modem inputs. This bit
/// is cleared to 0 on reset, to disable loopback.
pub enable_loopback: bool, pub enable_loopback: bool,
/// `TXE` Transmit enable. If this bit is set to 1, the transmit section /// `TXE` Transmit enable
/// of the UART is enabled. Data transmission occurs for either UART
/// signals, or SIR signals depending on the setting of the SIREN bit.
/// When the UART is disabled in the middle of transmission, it
/// completes the current character before stopping.
pub enable_transmit: bool, pub enable_transmit: bool,
/// `RXE` Receive enable. If this bit is set to 1, the receive section /// `RXE` Receive enable
/// of the UART is enabled. Data reception occurs for either UART
/// signals or SIR signals depending on the setting of the SIREN bit.
/// When the UART is disabled in the middle of reception, it completes
/// the current character before stopping.
pub enable_receive: bool, pub enable_receive: bool,
/// `DTR` Data transmit ready. This bit is the complement of the UART /// `DTR` Data transmit ready
/// data transmit ready, `nUARTDTR`, modem status output. That is, when
/// the bit is programmed to a 1 then `nUARTDTR` is LOW.
pub data_transmit_ready: bool, pub data_transmit_ready: bool,
/// `RTS` Request to send. This bit is the complement of the UART /// `RTS` Request to send
/// request to send, `nUARTRTS`, modem status output. That is, when the
/// bit is programmed to a 1 then `nUARTRTS` is LOW.
pub request_to_send: bool, pub request_to_send: bool,
/// `Out1` This bit is the complement of the UART Out1 (`nUARTOut1`) /// `Out1` UART Out1 signal; can be used as DCD
/// modem status output. That is, when the bit is programmed to a 1 the
/// output is 0. For DTE this can be used as Data Carrier Detect (DCD).
pub out_1: bool, pub out_1: bool,
/// `Out2` This bit is the complement of the UART Out2 (`nUARTOut2`) /// `Out2` UART Out2 signal; can be used as RI
/// modem status output. That is, when the bit is programmed to a 1, the
/// output is 0. For DTE this can be used as Ring Indicator (RI).
pub out_2: bool, pub out_2: bool,
/// `RTSEn` RTS hardware flow control enable. If this bit is set to 1, /// `RTSEn` RTS hardware flow control enable
/// RTS hardware flow control is enabled. Data is only requested when
/// there is space in the receive FIFO for it to be received.
pub rts_hardware_flow_control_enable: bool, pub rts_hardware_flow_control_enable: bool,
/// `CTSEn` CTS hardware flow control enable. If this bit is set to 1, /// `CTSEn` CTS hardware flow control enable
/// CTS hardware flow control is enabled. Data is only transmitted when
/// the `nUARTCTS` signal is asserted.
pub cts_hardware_flow_control_enable: bool, pub cts_hardware_flow_control_enable: bool,
/// 31:16 - Reserved, do not modify, read as zero. /// 31:16 - Reserved, do not modify, read as zero.
_reserved_zero_no_modify2: u16, _reserved_zero_no_modify2: u16,

6
target/arm/arch_dump.c
View file

@ -143,7 +143,6 @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
return 0; return 0;
} }
#ifdef TARGET_AARCH64
static off_t sve_zreg_offset(uint32_t vq, int n) static off_t sve_zreg_offset(uint32_t vq, int n)
{ {
off_t off = sizeof(struct aarch64_user_sve_header); off_t off = sizeof(struct aarch64_user_sve_header);
@ -231,7 +230,6 @@ static int aarch64_write_elf64_sve(WriteCoreDumpFunction f,
return 0; return 0;
} }
#endif
int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, DumpState *s) int cpuid, DumpState *s)
@ -273,11 +271,9 @@ int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
return ret; return ret;
} }
#ifdef TARGET_AARCH64
if (cpu_isar_feature(aa64_sve, cpu)) { if (cpu_isar_feature(aa64_sve, cpu)) {
ret = aarch64_write_elf64_sve(f, env, cpuid, s); ret = aarch64_write_elf64_sve(f, env, cpuid, s);
} }
#endif
return ret; return ret;
} }
@ -451,11 +447,9 @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
if (class == ELFCLASS64) { if (class == ELFCLASS64) {
note_size = AARCH64_PRSTATUS_NOTE_SIZE; note_size = AARCH64_PRSTATUS_NOTE_SIZE;
note_size += AARCH64_PRFPREG_NOTE_SIZE; note_size += AARCH64_PRFPREG_NOTE_SIZE;
#ifdef TARGET_AARCH64
if (cpu_isar_feature(aa64_sve, cpu)) { if (cpu_isar_feature(aa64_sve, cpu)) {
note_size += AARCH64_SVE_NOTE_SIZE(&cpu->env); note_size += AARCH64_SVE_NOTE_SIZE(&cpu->env);
} }
#endif
} else { } else {
note_size = ARM_PRSTATUS_NOTE_SIZE; note_size = ARM_PRSTATUS_NOTE_SIZE;
if (cpu_isar_feature(aa32_vfp_simd, cpu)) { if (cpu_isar_feature(aa32_vfp_simd, cpu)) {

5
target/arm/cpu-qom.h
View file

@ -28,11 +28,6 @@ OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU)
#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
#define TYPE_AARCH64_CPU "aarch64-cpu"
typedef struct AArch64CPUClass AArch64CPUClass;
DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
TYPE_AARCH64_CPU)
#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)

83
target/arm/cpu.c
View file

@ -23,6 +23,7 @@
#include "qemu/timer.h" #include "qemu/timer.h"
#include "qemu/log.h" #include "qemu/log.h"
#include "exec/page-vary.h" #include "exec/page-vary.h"
#include "exec/tswap.h"
#include "target/arm/idau.h" #include "target/arm/idau.h"
#include "qemu/module.h" #include "qemu/module.h"
#include "qapi/error.h" #include "qapi/error.h"
@ -1098,37 +1099,6 @@ static void arm_cpu_set_irq(void *opaque, int irq, int level)
} }
} }
static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
{
#ifdef CONFIG_KVM
ARMCPU *cpu = opaque;
CPUARMState *env = &cpu->env;
CPUState *cs = CPU(cpu);
uint32_t linestate_bit;
int irq_id;
switch (irq) {
case ARM_CPU_IRQ:
irq_id = KVM_ARM_IRQ_CPU_IRQ;
linestate_bit = CPU_INTERRUPT_HARD;
break;
case ARM_CPU_FIQ:
irq_id = KVM_ARM_IRQ_CPU_FIQ;
linestate_bit = CPU_INTERRUPT_FIQ;
break;
default:
g_assert_not_reached();
}
if (level) {
env->irq_line_state |= linestate_bit;
} else {
env->irq_line_state &= ~linestate_bit;
}
kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level);
#endif
}
static bool arm_cpu_virtio_is_big_endian(CPUState *cs) static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
{ {
ARMCPU *cpu = ARM_CPU(cs); ARMCPU *cpu = ARM_CPU(cs);
@ -1202,7 +1172,7 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
info->endian = BFD_ENDIAN_LITTLE; info->endian = BFD_ENDIAN_LITTLE;
if (bswap_code(sctlr_b)) { if (bswap_code(sctlr_b)) {
info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; info->endian = target_big_endian() ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
} }
info->flags &= ~INSN_ARM_BE32; info->flags &= ~INSN_ARM_BE32;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
@ -1212,8 +1182,6 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
#endif #endif
} }
#ifdef TARGET_AARCH64
static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{ {
ARMCPU *cpu = ARM_CPU(cs); ARMCPU *cpu = ARM_CPU(cs);
@ -1371,15 +1339,6 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
} }
} }
#else
static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
g_assert_not_reached();
}
#endif
static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{ {
ARMCPU *cpu = ARM_CPU(cs); ARMCPU *cpu = ARM_CPU(cs);
@ -1609,6 +1568,35 @@ static void arm_set_pmu(Object *obj, bool value, Error **errp)
cpu->has_pmu = value; cpu->has_pmu = value;
} }
static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
}
static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
/*
* At this time, this property is only allowed if KVM is enabled. This
* restriction allows us to avoid fixing up functionality that assumes a
* uniform execution state like do_interrupt.
*/
if (value == false) {
if (!kvm_enabled() || !kvm_arm_aarch32_supported()) {
error_setg(errp, "'aarch64' feature cannot be disabled "
"unless KVM is enabled and 32-bit EL1 "
"is supported");
return;
}
unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
} else {
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
}
}
unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
{ {
/* /*
@ -1736,6 +1724,13 @@ void arm_cpu_post_init(Object *obj)
*/ */
arm_cpu_propagate_feature_implications(cpu); arm_cpu_propagate_feature_implications(cpu);
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
aarch64_cpu_set_aarch64);
object_property_set_description(obj, "aarch64",
"Set on/off to enable/disable aarch64 "
"execution state ");
}
if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property);
@ -1918,7 +1913,6 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
{ {
Error *local_err = NULL; Error *local_err = NULL;
#ifdef TARGET_AARCH64
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
arm_cpu_sve_finalize(cpu, &local_err); arm_cpu_sve_finalize(cpu, &local_err);
if (local_err != NULL) { if (local_err != NULL) {
@ -1954,7 +1948,6 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
return; return;
} }
} }
#endif
if (kvm_enabled()) { if (kvm_enabled()) {
kvm_arm_steal_time_finalize(cpu, &local_err); kvm_arm_steal_time_finalize(cpu, &local_err);

4
target/arm/cpu.h
View file

@ -1138,10 +1138,6 @@ struct ARMCPUClass {
ResettablePhases parent_phases; ResettablePhases parent_phases;
}; };
struct AArch64CPUClass {
ARMCPUClass parent_class;
};
/* Callback functions for the generic timer's timers. */ /* Callback functions for the generic timer's timers. */
void arm_gt_ptimer_cb(void *opaque); void arm_gt_ptimer_cb(void *opaque);
void arm_gt_vtimer_cb(void *opaque); void arm_gt_vtimer_cb(void *opaque);

26
target/arm/cpu32-stubs.c Normal file
View file

@ -0,0 +1,26 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include "qemu/osdep.h"
#include "target/arm/cpu.h"
#include "target/arm/internals.h"
#include <glib.h>
void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp)
{
g_assert_not_reached();
}
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
{
g_assert_not_reached();
}
void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
{
g_assert_not_reached();
}
void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
{
g_assert_not_reached();
}

82
target/arm/cpu64.c
View file

@ -781,92 +781,12 @@ static const ARMCPUInfo aarch64_cpus[] = {
#endif #endif
}; };
static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
}
static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
/* At this time, this property is only allowed if KVM is enabled. This
* restriction allows us to avoid fixing up functionality that assumes a
* uniform execution state like do_interrupt.
*/
if (value == false) {
if (!kvm_enabled() || !kvm_arm_aarch32_supported()) {
error_setg(errp, "'aarch64' feature cannot be disabled "
"unless KVM is enabled and 32-bit EL1 "
"is supported");
return;
}
unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
} else {
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
}
}
static void aarch64_cpu_finalizefn(Object *obj)
{
}
static void aarch64_cpu_class_init(ObjectClass *oc, const void *data)
{
object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64,
aarch64_cpu_set_aarch64);
object_class_property_set_description(oc, "aarch64",
"Set on/off to enable/disable aarch64 "
"execution state ");
}
static void aarch64_cpu_instance_init(Object *obj)
{
ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
acc->info->initfn(obj);
arm_cpu_post_init(obj);
}
static void cpu_register_class_init(ObjectClass *oc, const void *data)
{
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
acc->info = data;
}
void aarch64_cpu_register(const ARMCPUInfo *info)
{
TypeInfo type_info = {
.parent = TYPE_AARCH64_CPU,
.instance_init = aarch64_cpu_instance_init,
.class_init = info->class_init ?: cpu_register_class_init,
.class_data = info,
};
type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
type_register_static(&type_info);
g_free((void *)type_info.name);
}
static const TypeInfo aarch64_cpu_type_info = {
.name = TYPE_AARCH64_CPU,
.parent = TYPE_ARM_CPU,
.instance_finalize = aarch64_cpu_finalizefn,
.abstract = true,
.class_init = aarch64_cpu_class_init,
};
static void aarch64_cpu_register_types(void) static void aarch64_cpu_register_types(void)
{ {
size_t i; size_t i;
type_register_static(&aarch64_cpu_type_info);
for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
aarch64_cpu_register(&aarch64_cpus[i]); arm_cpu_register(&aarch64_cpus[i]);
} }
} }

6
target/arm/debug_helper.c
View file

@ -11,10 +11,12 @@
#include "internals.h" #include "internals.h"
#include "cpu-features.h" #include "cpu-features.h"
#include "cpregs.h" #include "cpregs.h"
#include "exec/helper-proto.h"
#include "exec/watchpoint.h" #include "exec/watchpoint.h"
#include "system/tcg.h" #include "system/tcg.h"
#define HELPER_H "tcg/helper.h"
#include "exec/helper-proto.h.inc"
#ifdef CONFIG_TCG #ifdef CONFIG_TCG
/* Return the Exception Level targeted by debug exceptions. */ /* Return the Exception Level targeted by debug exceptions. */
static int arm_debug_target_el(CPUARMState *env) static int arm_debug_target_el(CPUARMState *env)
@ -378,7 +380,7 @@ bool arm_debug_check_breakpoint(CPUState *cs)
{ {
ARMCPU *cpu = ARM_CPU(cs); ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env; CPUARMState *env = &cpu->env;
target_ulong pc; vaddr pc;
int n; int n;
/* /*

24
target/arm/helper.c
View file

@ -12,7 +12,6 @@
#include "cpu.h" #include "cpu.h"
#include "internals.h" #include "internals.h"
#include "cpu-features.h" #include "cpu-features.h"
#include "exec/helper-proto.h"
#include "exec/page-protection.h" #include "exec/page-protection.h"
#include "exec/mmap-lock.h" #include "exec/mmap-lock.h"
#include "qemu/main-loop.h" #include "qemu/main-loop.h"
@ -30,11 +29,15 @@
#include "qemu/guest-random.h" #include "qemu/guest-random.h"
#ifdef CONFIG_TCG #ifdef CONFIG_TCG
#include "accel/tcg/probe.h" #include "accel/tcg/probe.h"
#include "accel/tcg/getpc.h"
#include "semihosting/common-semi.h" #include "semihosting/common-semi.h"
#endif #endif
#include "cpregs.h" #include "cpregs.h"
#include "target/arm/gtimer.h" #include "target/arm/gtimer.h"
#define HELPER_H "tcg/helper.h"
#include "exec/helper-proto.h.inc"
#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
static void switch_mode(CPUARMState *env, int mode); static void switch_mode(CPUARMState *env, int mode);
@ -6563,9 +6566,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
*/ */
new_len = sve_vqm1_for_el(env, cur_el); new_len = sve_vqm1_for_el(env, cur_el);
if (new_len < old_len) { if (new_len < old_len) {
#ifdef TARGET_AARCH64
aarch64_sve_narrow_vq(env, new_len + 1); aarch64_sve_narrow_vq(env, new_len + 1);
#endif
} }
} }
@ -6588,7 +6589,6 @@ static const ARMCPRegInfo zcr_reginfo[] = {
.writefn = zcr_write, .raw_writefn = raw_write }, .writefn = zcr_write, .raw_writefn = raw_write },
}; };
#ifdef TARGET_AARCH64
static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri, static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread) bool isread)
{ {
@ -6822,7 +6822,6 @@ static const ARMCPRegInfo nmi_reginfo[] = {
.writefn = aa64_allint_write, .readfn = aa64_allint_read, .writefn = aa64_allint_write, .readfn = aa64_allint_read,
.resetfn = arm_cp_reset_ignore }, .resetfn = arm_cp_reset_ignore },
}; };
#endif /* TARGET_AARCH64 */
static void define_pmu_regs(ARMCPU *cpu) static void define_pmu_regs(ARMCPU *cpu)
{ {
@ -7014,7 +7013,6 @@ static const ARMCPRegInfo lor_reginfo[] = {
.type = ARM_CP_CONST, .resetvalue = 0 }, .type = ARM_CP_CONST, .resetvalue = 0 },
}; };
#ifdef TARGET_AARCH64
static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri, static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread) bool isread)
{ {
@ -7507,8 +7505,6 @@ static const ARMCPRegInfo nv2_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.vncr_el2) }, .fieldoffset = offsetof(CPUARMState, cp15.vncr_el2) },
}; };
#endif /* TARGET_AARCH64 */
static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread) bool isread)
{ {
@ -7768,7 +7764,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, not_v8_cp_reginfo); define_arm_cp_regs(cpu, not_v8_cp_reginfo);
} }
#ifndef CONFIG_USER_ONLY
define_tlb_insn_regs(cpu); define_tlb_insn_regs(cpu);
#endif
if (arm_feature(env, ARM_FEATURE_V6)) { if (arm_feature(env, ARM_FEATURE_V6)) {
/* The ID registers all have impdef reset values */ /* The ID registers all have impdef reset values */
@ -8949,7 +8947,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_one_arm_cp_reg(cpu, &hcrx_el2_reginfo); define_one_arm_cp_reg(cpu, &hcrx_el2_reginfo);
} }
#ifdef TARGET_AARCH64
if (cpu_isar_feature(aa64_sme, cpu)) { if (cpu_isar_feature(aa64_sme, cpu)) {
define_arm_cp_regs(cpu, sme_reginfo); define_arm_cp_regs(cpu, sme_reginfo);
} }
@ -9010,7 +9007,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (cpu_isar_feature(aa64_nmi, cpu)) { if (cpu_isar_feature(aa64_nmi, cpu)) {
define_arm_cp_regs(cpu, nmi_reginfo); define_arm_cp_regs(cpu, nmi_reginfo);
} }
#endif
if (cpu_isar_feature(any_predinv, cpu)) { if (cpu_isar_feature(any_predinv, cpu)) {
define_arm_cp_regs(cpu, predinv_reginfo); define_arm_cp_regs(cpu, predinv_reginfo);
@ -10619,7 +10615,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
ARMCPU *cpu = ARM_CPU(cs); ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env; CPUARMState *env = &cpu->env;
unsigned int new_el = env->exception.target_el; unsigned int new_el = env->exception.target_el;
target_ulong addr = env->cp15.vbar_el[new_el]; vaddr addr = env->cp15.vbar_el[new_el];
unsigned int new_mode = aarch64_pstate_mode(new_el, true); unsigned int new_mode = aarch64_pstate_mode(new_el, true);
unsigned int old_mode; unsigned int old_mode;
unsigned int cur_el = arm_current_el(env); unsigned int cur_el = arm_current_el(env);
@ -10630,9 +10626,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
* Note that new_el can never be 0. If cur_el is 0, then * Note that new_el can never be 0. If cur_el is 0, then
* el0_a64 is is_a64(), else el0_a64 is ignored. * el0_a64 is is_a64(), else el0_a64 is ignored.
*/ */
#ifdef TARGET_AARCH64
aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
#endif
} }
if (cur_el < new_el) { if (cur_el < new_el) {
@ -11423,7 +11417,6 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env)
return arm_mmu_idx_el(env, arm_current_el(env)); return arm_mmu_idx_el(env, arm_current_el(env));
} }
#ifdef TARGET_AARCH64
/* /*
* The manual says that when SVE is enabled and VQ is widened the * The manual says that when SVE is enabled and VQ is widened the
* implementation is allowed to zero the previously inaccessible * implementation is allowed to zero the previously inaccessible
@ -11535,12 +11528,9 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el,
/* When changing vector length, clear inaccessible state. */ /* When changing vector length, clear inaccessible state. */
if (new_len < old_len) { if (new_len < old_len) {
#ifdef TARGET_AARCH64
aarch64_sve_narrow_vq(env, new_len + 1); aarch64_sve_narrow_vq(env, new_len + 1);
#endif
} }
} }
#endif
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
ARMSecuritySpace arm_security_space(CPUARMState *env) ARMSecuritySpace arm_security_space(CPUARMState *env)

1152
target/arm/helper.h
View file

File diff suppressed because it is too large Load diff

6
target/arm/hyp_gdbstub.c
View file

@ -54,7 +54,7 @@ GArray *hw_breakpoints, *hw_watchpoints;
* here so future PC comparisons will work properly. * here so future PC comparisons will work properly.
*/ */
int insert_hw_breakpoint(target_ulong addr) int insert_hw_breakpoint(vaddr addr)
{ {
HWBreakpoint brk = { HWBreakpoint brk = {
.bcr = 0x1, /* BCR E=1, enable */ .bcr = 0x1, /* BCR E=1, enable */
@ -80,7 +80,7 @@ int insert_hw_breakpoint(target_ulong addr)
* Delete a breakpoint and shuffle any above down * Delete a breakpoint and shuffle any above down
*/ */
int delete_hw_breakpoint(target_ulong pc) int delete_hw_breakpoint(vaddr pc)
{ {
int i; int i;
for (i = 0; i < hw_breakpoints->len; i++) { for (i = 0; i < hw_breakpoints->len; i++) {
@ -226,7 +226,7 @@ int delete_hw_watchpoint(vaddr addr, vaddr len, int type)
return -ENOENT; return -ENOENT;
} }
bool find_hw_breakpoint(CPUState *cpu, target_ulong pc) bool find_hw_breakpoint(CPUState *cpu, vaddr pc)
{ {
int i; int i;

9
target/arm/internals.h
View file

@ -354,7 +354,6 @@ static inline int r14_bank_number(int mode)
} }
void arm_cpu_register(const ARMCPUInfo *info); void arm_cpu_register(const ARMCPUInfo *info);
void aarch64_cpu_register(const ARMCPUInfo *info);
void register_cp_regs_for_features(ARMCPU *cpu); void register_cp_regs_for_features(ARMCPU *cpu);
void init_cpreg_list(ARMCPU *cpu); void init_cpreg_list(ARMCPU *cpu);
@ -1833,7 +1832,7 @@ void aarch64_add_sme_properties(Object *obj);
/* Return true if the gdbstub is presenting an AArch64 CPU */ /* Return true if the gdbstub is presenting an AArch64 CPU */
static inline bool arm_gdbstub_is_aarch64(ARMCPU *cpu) static inline bool arm_gdbstub_is_aarch64(ARMCPU *cpu)
{ {
return object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU); return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
} }
/* Read the CONTROL register as the MRS instruction would. */ /* Read the CONTROL register as the MRS instruction would. */
@ -1949,9 +1948,9 @@ extern GArray *hw_breakpoints, *hw_watchpoints;
#define get_hw_bp(i) (&g_array_index(hw_breakpoints, HWBreakpoint, i)) #define get_hw_bp(i) (&g_array_index(hw_breakpoints, HWBreakpoint, i))
#define get_hw_wp(i) (&g_array_index(hw_watchpoints, HWWatchpoint, i)) #define get_hw_wp(i) (&g_array_index(hw_watchpoints, HWWatchpoint, i))
bool find_hw_breakpoint(CPUState *cpu, target_ulong pc); bool find_hw_breakpoint(CPUState *cpu, vaddr pc);
int insert_hw_breakpoint(target_ulong pc); int insert_hw_breakpoint(vaddr pc);
int delete_hw_breakpoint(target_ulong pc); int delete_hw_breakpoint(vaddr pc);
bool check_watchpoint_in_range(int i, vaddr addr); bool check_watchpoint_in_range(int i, vaddr addr);
CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, vaddr addr); CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, vaddr addr);

97
target/arm/kvm-stub.c
View file

@ -22,3 +22,100 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
{ {
g_assert_not_reached(); g_assert_not_reached();
} }
/*
* It's safe to call these functions without KVM support.
* They should either do nothing or return "not supported".
*/
bool kvm_arm_aarch32_supported(void)
{
return false;
}
bool kvm_arm_pmu_supported(void)
{
return false;
}
bool kvm_arm_sve_supported(void)
{
return false;
}
bool kvm_arm_mte_supported(void)
{
return false;
}
/*
* These functions should never actually be called without KVM support.
*/
void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
{
g_assert_not_reached();
}
void kvm_arm_add_vcpu_properties(ARMCPU *cpu)
{
g_assert_not_reached();
}
int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa)
{
g_assert_not_reached();
}
int kvm_arm_vgic_probe(void)
{
g_assert_not_reached();
}
void kvm_arm_pmu_set_irq(ARMCPU *cpu, int irq)
{
g_assert_not_reached();
}
void kvm_arm_pmu_init(ARMCPU *cpu)
{
g_assert_not_reached();
}
void kvm_arm_pvtime_init(ARMCPU *cpu, uint64_t ipa)
{
g_assert_not_reached();
}
void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp)
{
g_assert_not_reached();
}
uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu)
{
g_assert_not_reached();
}
void kvm_arm_enable_mte(Object *cpuobj, Error **errp)
{
g_assert_not_reached();
}
void kvm_arm_reset_vcpu(ARMCPU *cpu)
{
g_assert_not_reached();
}
void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level)
{
g_assert_not_reached();
}
void kvm_arm_cpu_pre_save(ARMCPU *cpu)
{
g_assert_not_reached();
}
bool kvm_arm_cpu_post_load(ARMCPU *cpu)
{
g_assert_not_reached();
}

45
target/arm/kvm.c
View file

@ -938,13 +938,24 @@ void kvm_arm_cpu_pre_save(ARMCPU *cpu)
} }
} }
void kvm_arm_cpu_post_load(ARMCPU *cpu) bool kvm_arm_cpu_post_load(ARMCPU *cpu)
{ {
if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) {
return false;
}
/* Note that it's OK for the TCG side not to know about
* every register in the list; KVM is authoritative if
* we're using it.
*/
write_list_to_cpustate(cpu);
/* KVM virtual time adjustment */ /* KVM virtual time adjustment */
if (cpu->kvm_adjvtime) { if (cpu->kvm_adjvtime) {
cpu->kvm_vtime = *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT); cpu->kvm_vtime = *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT);
cpu->kvm_vtime_dirty = true; cpu->kvm_vtime_dirty = true;
} }
return true;
} }
void kvm_arm_reset_vcpu(ARMCPU *cpu) void kvm_arm_reset_vcpu(ARMCPU *cpu)
@ -1843,8 +1854,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
CPUARMState *env = &cpu->env; CPUARMState *env = &cpu->env;
uint64_t psciver; uint64_t psciver;
if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE || if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) {
!object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
error_report("KVM is not supported for this guest CPU type"); error_report("KVM is not supported for this guest CPU type");
return -EINVAL; return -EINVAL;
} }
@ -2429,3 +2439,32 @@ void kvm_arm_enable_mte(Object *cpuobj, Error **errp)
cpu->kvm_mte = true; cpu->kvm_mte = true;
} }
} }
void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level)
{
ARMCPU *cpu = arm_cpu;
CPUARMState *env = &cpu->env;
CPUState *cs = CPU(cpu);
uint32_t linestate_bit;
int irq_id;
switch (irq) {
case ARM_CPU_IRQ:
irq_id = KVM_ARM_IRQ_CPU_IRQ;
linestate_bit = CPU_INTERRUPT_HARD;
break;
case ARM_CPU_FIQ:
irq_id = KVM_ARM_IRQ_CPU_FIQ;
linestate_bit = CPU_INTERRUPT_FIQ;
break;
default:
g_assert_not_reached();
}
if (level) {
env->irq_line_state |= linestate_bit;
} else {
env->irq_line_state &= ~linestate_bit;
}
kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level);
}

87
target/arm/kvm_arm.h
View file

@ -83,8 +83,10 @@ void kvm_arm_cpu_pre_save(ARMCPU *cpu);
* @cpu: ARMCPU * @cpu: ARMCPU
* *
* Called from cpu_post_load() to update KVM CPU state from the cpreg list. * Called from cpu_post_load() to update KVM CPU state from the cpreg list.
*
* Returns: true on success, or false if write_list_to_kvmstate failed.
*/ */
void kvm_arm_cpu_post_load(ARMCPU *cpu); bool kvm_arm_cpu_post_load(ARMCPU *cpu);
/** /**
* kvm_arm_reset_vcpu: * kvm_arm_reset_vcpu:
@ -94,7 +96,7 @@ void kvm_arm_cpu_post_load(ARMCPU *cpu);
*/ */
void kvm_arm_reset_vcpu(ARMCPU *cpu); void kvm_arm_reset_vcpu(ARMCPU *cpu);
#ifdef CONFIG_KVM struct kvm_vcpu_init;
/** /**
* kvm_arm_create_scratch_host_vcpu: * kvm_arm_create_scratch_host_vcpu:
* @fdarray: filled in with kvmfd, vmfd, cpufd file descriptors in that order * @fdarray: filled in with kvmfd, vmfd, cpufd file descriptors in that order
@ -216,85 +218,6 @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level);
void kvm_arm_enable_mte(Object *cpuobj, Error **errp); void kvm_arm_enable_mte(Object *cpuobj, Error **errp);
#else void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level);
/*
* It's safe to call these functions without KVM support.
* They should either do nothing or return "not supported".
*/
static inline bool kvm_arm_aarch32_supported(void)
{
return false;
}
static inline bool kvm_arm_pmu_supported(void)
{
return false;
}
static inline bool kvm_arm_sve_supported(void)
{
return false;
}
static inline bool kvm_arm_mte_supported(void)
{
return false;
}
/*
* These functions should never actually be called without KVM support.
*/
static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
{
g_assert_not_reached();
}
static inline void kvm_arm_add_vcpu_properties(ARMCPU *cpu)
{
g_assert_not_reached();
}
static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa)
{
g_assert_not_reached();
}
static inline int kvm_arm_vgic_probe(void)
{
g_assert_not_reached();
}
static inline void kvm_arm_pmu_set_irq(ARMCPU *cpu, int irq)
{
g_assert_not_reached();
}
static inline void kvm_arm_pmu_init(ARMCPU *cpu)
{
g_assert_not_reached();
}
static inline void kvm_arm_pvtime_init(ARMCPU *cpu, uint64_t ipa)
{
g_assert_not_reached();
}
static inline void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp)
{
g_assert_not_reached();
}
static inline uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu)
{
g_assert_not_reached();
}
static inline void kvm_arm_enable_mte(Object *cpuobj, Error **errp)
{
g_assert_not_reached();
}
#endif
#endif #endif

15
target/arm/machine.c
View file

@ -6,7 +6,8 @@
#include "kvm_arm.h" #include "kvm_arm.h"
#include "internals.h" #include "internals.h"
#include "cpu-features.h" #include "cpu-features.h"
#include "migration/cpu.h" #include "migration/qemu-file-types.h"
#include "migration/vmstate.h"
#include "target/arm/gtimer.h" #include "target/arm/gtimer.h"
static bool vfp_needed(void *opaque) static bool vfp_needed(void *opaque)
@ -240,7 +241,6 @@ static const VMStateDescription vmstate_iwmmxt = {
} }
}; };
#ifdef TARGET_AARCH64
/* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build, /* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build,
* and ARMPredicateReg is actively empty. This triggers errors * and ARMPredicateReg is actively empty. This triggers errors
* in the expansion of the VMSTATE macros. * in the expansion of the VMSTATE macros.
@ -320,7 +320,6 @@ static const VMStateDescription vmstate_za = {
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };
#endif /* AARCH64 */
static bool serror_needed(void *opaque) static bool serror_needed(void *opaque)
{ {
@ -977,15 +976,9 @@ static int cpu_post_load(void *opaque, int version_id)
} }
if (kvm_enabled()) { if (kvm_enabled()) {
if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { if (!kvm_arm_cpu_post_load(cpu)) {
return -1; return -1;
} }
/* Note that it's OK for the TCG side not to know about
* every register in the list; KVM is authoritative if
* we're using it.
*/
write_list_to_cpustate(cpu);
kvm_arm_cpu_post_load(cpu);
} else { } else {
if (!write_list_to_cpustate(cpu)) { if (!write_list_to_cpustate(cpu)) {
return -1; return -1;
@ -1101,10 +1094,8 @@ const VMStateDescription vmstate_arm_cpu = {
&vmstate_pmsav7, &vmstate_pmsav7,
&vmstate_pmsav8, &vmstate_pmsav8,
&vmstate_m_security, &vmstate_m_security,
#ifdef TARGET_AARCH64
&vmstate_sve, &vmstate_sve,
&vmstate_za, &vmstate_za,
#endif
&vmstate_serror, &vmstate_serror,
&vmstate_irq_line_state, &vmstate_irq_line_state,
&vmstate_wfxt_timer, &vmstate_wfxt_timer,

45
target/arm/meson.build
View file

@ -1,32 +1,47 @@
arm_ss = ss.source_set() arm_ss = ss.source_set()
arm_common_ss = ss.source_set()
arm_ss.add(files( arm_ss.add(files(
'cpu.c',
'debug_helper.c',
'gdbstub.c', 'gdbstub.c',
'helper.c',
'vfp_fpscr.c',
)) ))
arm_ss.add(zlib) arm_ss.add(zlib)
arm_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'), if_false: files('kvm-stub.c'))
arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c'))
arm_ss.add(when: 'TARGET_AARCH64', if_true: files( arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
'cpu64.c', 'cpu64.c',
'gdbstub64.c', 'gdbstub64.c'))
))
arm_system_ss = ss.source_set() arm_system_ss = ss.source_set()
arm_common_system_ss = ss.source_set()
arm_system_ss.add(files( arm_system_ss.add(files(
'arch_dump.c',
'arm-powerctl.c',
'arm-qmp-cmds.c', 'arm-qmp-cmds.c',
'cortex-regs.c',
'machine.c',
'ptw.c',
)) ))
arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'))
arm_system_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c'))
arm_user_ss = ss.source_set() arm_user_ss = ss.source_set()
arm_user_ss.add(files('cpu.c'))
arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files(
'cpu32-stubs.c',
))
arm_user_ss.add(files(
'debug_helper.c',
'helper.c',
'vfp_fpscr.c',
))
arm_common_system_ss.add(files('cpu.c'), capstone)
arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files(
'cpu32-stubs.c'))
arm_common_system_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c'))
arm_common_system_ss.add(files(
'arch_dump.c',
'arm-powerctl.c',
'cortex-regs.c',
'debug_helper.c',
'helper.c',
'machine.c',
'ptw.c',
'vfp_fpscr.c',
))
subdir('hvf') subdir('hvf')
@ -39,3 +54,5 @@ endif
target_arch += {'arm': arm_ss} target_arch += {'arm': arm_ss}
target_system_arch += {'arm': arm_system_ss} target_system_arch += {'arm': arm_system_ss}
target_user_arch += {'arm': arm_user_ss} target_user_arch += {'arm': arm_user_ss}
target_common_arch += {'arm': arm_common_ss}
target_common_system_arch += {'arm': arm_common_system_ss}

6
target/arm/ptw.c
View file

@ -737,7 +737,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val,
uint64_t new_val, S1Translate *ptw, uint64_t new_val, S1Translate *ptw,
ARMMMUFaultInfo *fi) ARMMMUFaultInfo *fi)
{ {
#if defined(TARGET_AARCH64) && defined(CONFIG_TCG) #if defined(CONFIG_ATOMIC64) && defined(CONFIG_TCG)
uint64_t cur_val; uint64_t cur_val;
void *host = ptw->out_host; void *host = ptw->out_host;
@ -1660,7 +1660,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
uint64_t ttbr; uint64_t ttbr;
hwaddr descaddr, indexmask, indexmask_grainsize; hwaddr descaddr, indexmask, indexmask_grainsize;
uint32_t tableattrs; uint32_t tableattrs;
target_ulong page_size; uint64_t page_size;
uint64_t attrs; uint64_t attrs;
int32_t stride; int32_t stride;
int addrsize, inputsize, outputsize; int addrsize, inputsize, outputsize;
@ -1733,7 +1733,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
* validation to do here. * validation to do here.
*/ */
if (inputsize < addrsize) { if (inputsize < addrsize) {
target_ulong top_bits = sextract64(address, inputsize, uint64_t top_bits = sextract64(address, inputsize,
addrsize - inputsize); addrsize - inputsize);
if (-top_bits != param.select) { if (-top_bits != param.select) {
/* The gap between the two regions is a Translation fault */ /* The gap between the two regions is a Translation fault */

5
target/arm/tcg/arith_helper.c
View file

@ -6,11 +6,12 @@
* SPDX-License-Identifier: GPL-2.0-or-later * SPDX-License-Identifier: GPL-2.0-or-later
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "cpu.h"
#include "exec/helper-proto.h"
#include "qemu/crc32c.h" #include "qemu/crc32c.h"
#include <zlib.h> /* for crc32 */ #include <zlib.h> /* for crc32 */
#define HELPER_H "tcg/helper.h"
#include "exec/helper-proto.h.inc"
/* /*
* Note that signed overflow is undefined in C. The following routines are * Note that signed overflow is undefined in C. The following routines are
* careful to use unsigned types where modulo arithmetic is required. * careful to use unsigned types where modulo arithmetic is required.

2
target/arm/tcg/cpu64.c
View file

@ -1316,7 +1316,7 @@ static void aarch64_cpu_register_types(void)
size_t i; size_t i;
for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
aarch64_cpu_register(&aarch64_cpus[i]); arm_cpu_register(&aarch64_cpus[i]);
} }
} }

6
target/arm/tcg/crypto_helper.c
View file

@ -10,14 +10,16 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/bitops.h"
#include "cpu.h"
#include "exec/helper-proto.h"
#include "tcg/tcg-gvec-desc.h" #include "tcg/tcg-gvec-desc.h"
#include "crypto/aes-round.h" #include "crypto/aes-round.h"
#include "crypto/sm4.h" #include "crypto/sm4.h"
#include "vec_internal.h" #include "vec_internal.h"
#define HELPER_H "tcg/helper.h"
#include "exec/helper-proto.h.inc"
union CRYPTO_STATE { union CRYPTO_STATE {
uint8_t bytes[16]; uint8_t bytes[16];
uint32_t words[4]; uint32_t words[4];

1153
target/arm/tcg/helper.h Normal file
View file

File diff suppressed because it is too large Load diff

4
target/arm/tcg/hflags.c
View file

@ -9,11 +9,13 @@
#include "cpu.h" #include "cpu.h"
#include "internals.h" #include "internals.h"
#include "cpu-features.h" #include "cpu-features.h"
#include "exec/helper-proto.h"
#include "exec/translation-block.h" #include "exec/translation-block.h"
#include "accel/tcg/cpu-ops.h" #include "accel/tcg/cpu-ops.h"
#include "cpregs.h" #include "cpregs.h"
#define HELPER_H "tcg/helper.h"
#include "exec/helper-proto.h.inc"
static inline bool fgt_svc(CPUARMState *env, int el) static inline bool fgt_svc(CPUARMState *env, int el)
{ {
/* /*

4
target/arm/tcg/iwmmxt_helper.c
View file

@ -22,7 +22,9 @@
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "cpu.h" #include "cpu.h"
#include "exec/helper-proto.h"
#define HELPER_H "tcg/helper.h"
#include "exec/helper-proto.h.inc"
/* iwMMXt macros extracted from GNU gdb. */ /* iwMMXt macros extracted from GNU gdb. */

29
target/arm/tcg/meson.build
View file

@ -30,18 +30,10 @@ arm_ss.add(files(
'translate-mve.c', 'translate-mve.c',
'translate-neon.c', 'translate-neon.c',
'translate-vfp.c', 'translate-vfp.c',
'crypto_helper.c',
'hflags.c',
'iwmmxt_helper.c',
'm_helper.c', 'm_helper.c',
'mve_helper.c', 'mve_helper.c',
'neon_helper.c',
'op_helper.c', 'op_helper.c',
'tlb_helper.c',
'vec_helper.c', 'vec_helper.c',
'tlb-insns.c',
'arith_helper.c',
'vfp_helper.c',
)) ))
arm_ss.add(when: 'TARGET_AARCH64', if_true: files( arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
@ -63,3 +55,24 @@ arm_system_ss.add(files(
arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c')) arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c'))
arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c')) arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c'))
arm_common_ss.add(files(
'arith_helper.c',
'crypto_helper.c',
))
arm_common_system_ss.add(files(
'hflags.c',
'iwmmxt_helper.c',
'neon_helper.c',
'tlb_helper.c',
'tlb-insns.c',
'vfp_helper.c',
))
arm_user_ss.add(files(
'hflags.c',
'iwmmxt_helper.c',
'neon_helper.c',
'tlb_helper.c',
'vfp_helper.c',
))

4
target/arm/tcg/neon_helper.c
View file

@ -9,11 +9,13 @@
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "cpu.h" #include "cpu.h"
#include "exec/helper-proto.h"
#include "tcg/tcg-gvec-desc.h" #include "tcg/tcg-gvec-desc.h"
#include "fpu/softfloat.h" #include "fpu/softfloat.h"
#include "vec_internal.h" #include "vec_internal.h"
#define HELPER_H "tcg/helper.h"
#include "exec/helper-proto.h.inc"
#define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT (uint32_t)0x80000000
#define SIGNBIT64 ((uint64_t)1 << 63) #define SIGNBIT64 ((uint64_t)1 << 63)

2
target/arm/tcg/op_helper.c
View file

@ -1222,7 +1222,7 @@ uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
} }
} }
void HELPER(probe_access)(CPUARMState *env, target_ulong ptr, void HELPER(probe_access)(CPUARMState *env, vaddr ptr,
uint32_t access_type, uint32_t mmu_idx, uint32_t access_type, uint32_t mmu_idx,
uint32_t size) uint32_t size)
{ {

7
target/arm/tcg/tlb-insns.c
View file

@ -35,7 +35,6 @@ static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri,
return CP_ACCESS_OK; return CP_ACCESS_OK;
} }
#ifdef TARGET_AARCH64
/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */ /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri, static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread) bool isread)
@ -46,7 +45,6 @@ static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri,
} }
return CP_ACCESS_OK; return CP_ACCESS_OK;
} }
#endif
/* IS variants of TLB operations must affect all cores */ /* IS variants of TLB operations must affect all cores */
static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -802,7 +800,6 @@ static const ARMCPRegInfo tlbi_el3_cp_reginfo[] = {
.writefn = tlbi_aa64_vae3_write }, .writefn = tlbi_aa64_vae3_write },
}; };
#ifdef TARGET_AARCH64
typedef struct { typedef struct {
uint64_t base; uint64_t base;
uint64_t length; uint64_t length;
@ -1270,8 +1267,6 @@ static const ARMCPRegInfo tlbi_rme_reginfo[] = {
.writefn = tlbi_aa64_paallos_write }, .writefn = tlbi_aa64_paallos_write },
}; };
#endif
void define_tlb_insn_regs(ARMCPU *cpu) void define_tlb_insn_regs(ARMCPU *cpu)
{ {
CPUARMState *env = &cpu->env; CPUARMState *env = &cpu->env;
@ -1299,7 +1294,6 @@ void define_tlb_insn_regs(ARMCPU *cpu)
if (arm_feature(env, ARM_FEATURE_EL3)) { if (arm_feature(env, ARM_FEATURE_EL3)) {
define_arm_cp_regs(cpu, tlbi_el3_cp_reginfo); define_arm_cp_regs(cpu, tlbi_el3_cp_reginfo);
} }
#ifdef TARGET_AARCH64
if (cpu_isar_feature(aa64_tlbirange, cpu)) { if (cpu_isar_feature(aa64_tlbirange, cpu)) {
define_arm_cp_regs(cpu, tlbirange_reginfo); define_arm_cp_regs(cpu, tlbirange_reginfo);
} }
@ -1309,5 +1303,4 @@ void define_tlb_insn_regs(ARMCPU *cpu)
if (cpu_isar_feature(aa64_rme, cpu)) { if (cpu_isar_feature(aa64_rme, cpu)) {
define_arm_cp_regs(cpu, tlbi_rme_reginfo); define_arm_cp_regs(cpu, tlbi_rme_reginfo);
} }
#endif
} }

5
target/arm/tcg/tlb_helper.c
View file

@ -9,8 +9,9 @@
#include "cpu.h" #include "cpu.h"
#include "internals.h" #include "internals.h"
#include "cpu-features.h" #include "cpu-features.h"
#include "exec/helper-proto.h"
#define HELPER_H "tcg/helper.h"
#include "exec/helper-proto.h.inc"
/* /*
* Returns true if the stage 1 translation regime is using LPAE format page * Returns true if the stage 1 translation regime is using LPAE format page
@ -276,7 +277,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
} }
void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) void helper_exception_pc_alignment(CPUARMState *env, vaddr pc)
{ {
ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; ARMMMUFaultInfo fi = { .type = ARMFault_Alignment };
int target_el = exception_target_el(env); int target_el = exception_target_el(env);

2
target/arm/tcg/translate-a64.c
View file

@ -10242,7 +10242,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
* start of the TB. * start of the TB.
*/ */
assert(s->base.num_insns == 1); assert(s->base.num_insns == 1);
gen_helper_exception_pc_alignment(tcg_env, tcg_constant_tl(pc)); gen_helper_exception_pc_alignment(tcg_env, tcg_constant_vaddr(pc));
s->base.is_jmp = DISAS_NORETURN; s->base.is_jmp = DISAS_NORETURN;
s->base.pc_next = QEMU_ALIGN_UP(pc, 4); s->base.pc_next = QEMU_ALIGN_UP(pc, 4);
return; return;

2
target/arm/tcg/translate.c
View file

@ -7791,7 +7791,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
* be possible after an indirect branch, at the start of the TB. * be possible after an indirect branch, at the start of the TB.
*/ */
assert(dc->base.num_insns == 1); assert(dc->base.num_insns == 1);
gen_helper_exception_pc_alignment(tcg_env, tcg_constant_tl(pc)); gen_helper_exception_pc_alignment(tcg_env, tcg_constant_vaddr(pc));
dc->base.is_jmp = DISAS_NORETURN; dc->base.is_jmp = DISAS_NORETURN;
dc->base.pc_next = QEMU_ALIGN_UP(pc, 4); dc->base.pc_next = QEMU_ALIGN_UP(pc, 4);
return; return;

2
target/arm/tcg/vec_internal.h
View file

@ -22,6 +22,8 @@
#include "fpu/softfloat.h" #include "fpu/softfloat.h"
typedef struct CPUArchState CPUARMState;
/* /*
* Note that vector data is stored in host-endian 64-bit chunks, * Note that vector data is stored in host-endian 64-bit chunks,
* so addressing units smaller than that needs a host-endian fixup. * so addressing units smaller than that needs a host-endian fixup.

4
target/arm/tcg/vfp_helper.c
View file

@ -19,12 +19,14 @@
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "cpu.h" #include "cpu.h"
#include "exec/helper-proto.h"
#include "internals.h" #include "internals.h"
#include "cpu-features.h" #include "cpu-features.h"
#include "fpu/softfloat.h" #include "fpu/softfloat.h"
#include "qemu/log.h" #include "qemu/log.h"
#define HELPER_H "tcg/helper.h"
#include "exec/helper-proto.h.inc"
/* /*
* Set the float_status behaviour to match the Arm defaults: * Set the float_status behaviour to match the Arm defaults:
* * tininess-before-rounding * * tininess-before-rounding

22
target/microblaze/cpu.c
View file

@ -263,6 +263,11 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
return; return;
} }
gdb_register_coprocessor(cs, mb_cpu_gdb_read_stack_protect,
mb_cpu_gdb_write_stack_protect,
gdb_find_static_feature("microblaze-stack-protect.xml"),
0);
qemu_init_vcpu(cs); qemu_init_vcpu(cs);
version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION; version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION;
@ -335,20 +340,13 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
static void mb_cpu_initfn(Object *obj) static void mb_cpu_initfn(Object *obj)
{ {
MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect,
mb_cpu_gdb_write_stack_protect,
gdb_find_static_feature("microblaze-stack-protect.xml"),
0);
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
/* Inbound IRQ and FIR lines */ /* Inbound IRQ and FIR lines */
qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); qdev_init_gpio_in(DEVICE(obj), microblaze_cpu_set_irq, 2);
qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1); qdev_init_gpio_in_named(DEVICE(obj), mb_cpu_ns_axi_dp, "ns_axi_dp", 1);
qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1); qdev_init_gpio_in_named(DEVICE(obj), mb_cpu_ns_axi_ip, "ns_axi_ip", 1);
qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1); qdev_init_gpio_in_named(DEVICE(obj), mb_cpu_ns_axi_dc, "ns_axi_dc", 1);
qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1); qdev_init_gpio_in_named(DEVICE(obj), mb_cpu_ns_axi_ic, "ns_axi_ic", 1);
#endif #endif
/* Restricted 'endianness' property is equivalent of 'little-endian' */ /* Restricted 'endianness' property is equivalent of 'little-endian' */

5
tcg/tcg.c
View file

@ -2367,6 +2367,11 @@ TCGv_i64 tcg_constant_i64(int64_t val)
return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val));
} }
TCGv_vaddr tcg_constant_vaddr(uintptr_t val)
{
return temp_tcgv_vaddr(tcg_constant_internal(TCG_TYPE_PTR, val));
}
TCGv_ptr tcg_constant_ptr_int(intptr_t val) TCGv_ptr tcg_constant_ptr_int(intptr_t val)
{ {
return temp_tcgv_ptr(tcg_constant_internal(TCG_TYPE_PTR, val)); return temp_tcgv_ptr(tcg_constant_internal(TCG_TYPE_PTR, val));