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tcg: Merge INDEX_op_not_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
592982bf04
commit
5c62d3779b
7 changed files with 24 additions and 29 deletions
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@ -315,7 +315,7 @@ Logical
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- | *t0* = *t1* ^ *t2*
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* - not_i32/i64 *t0*, *t1*
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* - not *t0*, *t1*
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- | *t0* = ~\ *t1*
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@ -46,6 +46,7 @@ DEF(eqv, 1, 2, 0, TCG_OPF_INT)
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DEF(nand, 1, 2, 0, TCG_OPF_INT)
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DEF(neg, 1, 1, 0, TCG_OPF_INT)
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DEF(nor, 1, 2, 0, TCG_OPF_INT)
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DEF(not, 1, 1, 0, TCG_OPF_INT)
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DEF(or, 1, 2, 0, TCG_OPF_INT)
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DEF(orc, 1, 2, 0, TCG_OPF_INT)
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DEF(sub, 1, 2, 0, TCG_OPF_INT)
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@ -95,7 +96,6 @@ DEF(setcond2_i32, 1, 4, 1, 0)
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DEF(bswap16_i32, 1, 1, 1, 0)
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DEF(bswap32_i32, 1, 1, 1, 0)
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DEF(not_i32, 1, 1, 0, 0)
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DEF(clz_i32, 1, 2, 0, 0)
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DEF(ctz_i32, 1, 2, 0, 0)
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DEF(ctpop_i32, 1, 1, 0, 0)
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@ -144,7 +144,6 @@ DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
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DEF(bswap16_i64, 1, 1, 1, 0)
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DEF(bswap32_i64, 1, 1, 1, 0)
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DEF(bswap64_i64, 1, 1, 1, 0)
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DEF(not_i64, 1, 1, 0, 0)
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DEF(clz_i64, 1, 2, 0, 0)
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DEF(ctz_i64, 1, 2, 0, 0)
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DEF(ctpop_i64, 1, 1, 0, 0)
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@ -475,7 +475,8 @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
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case INDEX_op_rotl_i64:
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return rol64(x, y & 63);
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CASE_OP_32_64_VEC(not):
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case INDEX_op_not:
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case INDEX_op_not_vec:
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return ~x;
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case INDEX_op_neg:
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@ -1103,12 +1104,9 @@ static bool fold_to_not(OptContext *ctx, TCGOp *op, int idx)
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switch (ctx->type) {
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case TCG_TYPE_I32:
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not_op = INDEX_op_not_i32;
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have_not = tcg_op_supported(INDEX_op_not_i32, TCG_TYPE_I32, 0);
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break;
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case TCG_TYPE_I64:
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not_op = INDEX_op_not_i64;
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have_not = tcg_op_supported(INDEX_op_not_i64, TCG_TYPE_I64, 0);
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not_op = INDEX_op_not;
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have_not = tcg_op_supported(INDEX_op_not, ctx->type, 0);
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break;
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case TCG_TYPE_V64:
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case TCG_TYPE_V128:
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@ -2987,7 +2985,8 @@ void tcg_optimize(TCGContext *s)
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case INDEX_op_nor_vec:
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done = fold_nor(&ctx, op);
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break;
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CASE_OP_32_64_VEC(not):
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case INDEX_op_not:
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case INDEX_op_not_vec:
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done = fold_not(&ctx, op);
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break;
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case INDEX_op_or:
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16
tcg/tcg-op.c
16
tcg/tcg-op.c
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@ -462,9 +462,9 @@ void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
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if (arg2 == 0) {
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tcg_gen_mov_i32(ret, arg1);
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} else if (arg2 == -1 &&
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tcg_op_supported(INDEX_op_not_i32, TCG_TYPE_I32, 0)) {
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tcg_op_supported(INDEX_op_not, TCG_TYPE_I32, 0)) {
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/* Don't recurse with tcg_gen_not_i32. */
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tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg1);
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tcg_gen_op2_i32(INDEX_op_not, ret, arg1);
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} else {
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tcg_gen_xor_i32(ret, arg1, tcg_constant_i32(arg2));
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}
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@ -472,8 +472,8 @@ void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
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void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
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{
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if (tcg_op_supported(INDEX_op_not_i32, TCG_TYPE_I32, 0)) {
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tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
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if (tcg_op_supported(INDEX_op_not, TCG_TYPE_I32, 0)) {
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tcg_gen_op2_i32(INDEX_op_not, ret, arg);
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} else {
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tcg_gen_xori_i32(ret, arg, -1);
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}
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@ -1764,9 +1764,9 @@ void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
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if (arg2 == 0) {
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tcg_gen_mov_i64(ret, arg1);
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} else if (arg2 == -1 &&
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tcg_op_supported(INDEX_op_not_i64, TCG_TYPE_I64, 0)) {
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tcg_op_supported(INDEX_op_not, TCG_TYPE_I64, 0)) {
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/* Don't recurse with tcg_gen_not_i64. */
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tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg1);
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tcg_gen_op2_i64(INDEX_op_not, ret, arg1);
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} else {
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tcg_gen_xor_i64(ret, arg1, tcg_constant_i64(arg2));
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}
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@ -2254,8 +2254,8 @@ void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
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if (TCG_TARGET_REG_BITS == 32) {
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tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg));
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tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
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} else if (tcg_op_supported(INDEX_op_not_i64, TCG_TYPE_I64, 0)) {
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tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
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} else if (tcg_op_supported(INDEX_op_not, TCG_TYPE_I64, 0)) {
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tcg_gen_op2_i64(INDEX_op_not, ret, arg);
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} else {
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tcg_gen_xori_i64(ret, arg, -1);
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}
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@ -1024,8 +1024,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
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OUTOP(INDEX_op_nand, TCGOutOpBinary, outop_nand),
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OUTOP(INDEX_op_neg, TCGOutOpUnary, outop_neg),
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OUTOP(INDEX_op_nor, TCGOutOpBinary, outop_nor),
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OUTOP(INDEX_op_not_i32, TCGOutOpUnary, outop_not),
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OUTOP(INDEX_op_not_i64, TCGOutOpUnary, outop_not),
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OUTOP(INDEX_op_not, TCGOutOpUnary, outop_not),
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OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or),
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OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc),
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OUTOP(INDEX_op_sub, TCGOutOpSubtract, outop_sub),
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@ -5474,8 +5473,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
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break;
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case INDEX_op_neg:
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case INDEX_op_not_i32:
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case INDEX_op_not_i64:
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case INDEX_op_not:
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{
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const TCGOutOpUnary *out =
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container_of(all_outop[op->opc], TCGOutOpUnary, base);
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11
tcg/tci.c
11
tcg/tci.c
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@ -571,6 +571,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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tci_args_rr(insn, &r0, &r1);
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regs[r0] = -regs[r1];
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break;
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case INDEX_op_not:
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tci_args_rr(insn, &r0, &r1);
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regs[r0] = ~regs[r1];
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break;
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/* Arithmetic operations (32 bit). */
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@ -695,10 +699,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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regs[r0] = bswap32(regs[r1]);
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break;
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#endif
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CASE_32_64(not)
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tci_args_rr(insn, &r0, &r1);
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regs[r0] = ~regs[r1];
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break;
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#if TCG_TARGET_REG_BITS == 64
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/* Load/store operations (64 bit). */
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@ -1053,6 +1053,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
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case INDEX_op_mov:
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case INDEX_op_neg:
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case INDEX_op_not:
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case INDEX_op_ext_i32_i64:
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case INDEX_op_extu_i32_i64:
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case INDEX_op_bswap16_i32:
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@ -1060,8 +1061,6 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
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case INDEX_op_bswap32_i32:
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case INDEX_op_bswap32_i64:
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case INDEX_op_bswap64_i64:
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case INDEX_op_not_i32:
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case INDEX_op_not_i64:
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case INDEX_op_ctpop_i32:
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case INDEX_op_ctpop_i64:
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tci_args_rr(insn, &r0, &r1);
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@ -739,7 +739,7 @@ static const TCGOutOpUnary outop_neg = {
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static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
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{
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tcg_out_op_rr(s, glue(INDEX_op_not_i,TCG_TARGET_REG_BITS), a0, a1);
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tcg_out_op_rr(s, INDEX_op_not, a0, a1);
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}
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static const TCGOutOpUnary outop_not = {
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