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tcg: Merge INDEX_op_eqv_{i32,i64}

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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-06 15:47:53 -08:00
parent 18bc920916
commit 5c0968a7e1
7 changed files with 15 additions and 17 deletions
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2
docs/devel/tcg-ops.rst
View file

@ -323,7 +323,7 @@ Logical
- | *t0* = *t1* & ~\ *t2* - | *t0* = *t1* & ~\ *t2*
* - eqv_i32/i64 *t0*, *t1*, *t2* * - eqv *t0*, *t1*, *t2*
- | *t0* = ~(*t1* ^ *t2*), or equivalently, *t0* = *t1* ^ ~\ *t2* - | *t0* = ~(*t1* ^ *t2*), or equivalently, *t0* = *t1* ^ ~\ *t2*

3
include/tcg/tcg-opc.h
View file

@ -42,6 +42,7 @@ DEF(mov, 1, 1, 0, TCG_OPF_INT | TCG_OPF_NOT_PRESENT)
DEF(add, 1, 2, 0, TCG_OPF_INT) DEF(add, 1, 2, 0, TCG_OPF_INT)
DEF(and, 1, 2, 0, TCG_OPF_INT) DEF(and, 1, 2, 0, TCG_OPF_INT)
DEF(andc, 1, 2, 0, TCG_OPF_INT) DEF(andc, 1, 2, 0, TCG_OPF_INT)
DEF(eqv, 1, 2, 0, TCG_OPF_INT)
DEF(or, 1, 2, 0, TCG_OPF_INT) DEF(or, 1, 2, 0, TCG_OPF_INT)
DEF(orc, 1, 2, 0, TCG_OPF_INT) DEF(orc, 1, 2, 0, TCG_OPF_INT)
DEF(xor, 1, 2, 0, TCG_OPF_INT) DEF(xor, 1, 2, 0, TCG_OPF_INT)
@ -93,7 +94,6 @@ DEF(bswap16_i32, 1, 1, 1, 0)
DEF(bswap32_i32, 1, 1, 1, 0) DEF(bswap32_i32, 1, 1, 1, 0)
DEF(not_i32, 1, 1, 0, 0) DEF(not_i32, 1, 1, 0, 0)
DEF(neg_i32, 1, 1, 0, 0) DEF(neg_i32, 1, 1, 0, 0)
DEF(eqv_i32, 1, 2, 0, 0)
DEF(nand_i32, 1, 2, 0, 0) DEF(nand_i32, 1, 2, 0, 0)
DEF(nor_i32, 1, 2, 0, 0) DEF(nor_i32, 1, 2, 0, 0)
DEF(clz_i32, 1, 2, 0, 0) DEF(clz_i32, 1, 2, 0, 0)
@ -147,7 +147,6 @@ DEF(bswap32_i64, 1, 1, 1, 0)
DEF(bswap64_i64, 1, 1, 1, 0) DEF(bswap64_i64, 1, 1, 1, 0)
DEF(not_i64, 1, 1, 0, 0) DEF(not_i64, 1, 1, 0, 0)
DEF(neg_i64, 1, 1, 0, 0) DEF(neg_i64, 1, 1, 0, 0)
DEF(eqv_i64, 1, 2, 0, 0)
DEF(nand_i64, 1, 2, 0, 0) DEF(nand_i64, 1, 2, 0, 0)
DEF(nor_i64, 1, 2, 0, 0) DEF(nor_i64, 1, 2, 0, 0)
DEF(clz_i64, 1, 2, 0, 0) DEF(clz_i64, 1, 2, 0, 0)

6
tcg/optimize.c
View file

@ -489,7 +489,8 @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
case INDEX_op_orc_vec: case INDEX_op_orc_vec:
return x | ~y; return x | ~y;
CASE_OP_32_64_VEC(eqv): case INDEX_op_eqv:
case INDEX_op_eqv_vec:
return ~(x ^ y); return ~(x ^ y);
CASE_OP_32_64_VEC(nand): CASE_OP_32_64_VEC(nand):
@ -2929,7 +2930,8 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_dup2_vec: case INDEX_op_dup2_vec:
done = fold_dup2(&ctx, op); done = fold_dup2(&ctx, op);
break; break;
CASE_OP_32_64_VEC(eqv): case INDEX_op_eqv:
case INDEX_op_eqv_vec:
done = fold_eqv(&ctx, op); done = fold_eqv(&ctx, op);
break; break;
CASE_OP_32_64(extract): CASE_OP_32_64(extract):

8
tcg/tcg-op.c
View file

@ -680,8 +680,8 @@ void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{ {
if (tcg_op_supported(INDEX_op_eqv_i32, TCG_TYPE_I32, 0)) { if (tcg_op_supported(INDEX_op_eqv, TCG_TYPE_I32, 0)) {
tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2); tcg_gen_op3_i32(INDEX_op_eqv, ret, arg1, arg2);
} else { } else {
tcg_gen_xor_i32(ret, arg1, arg2); tcg_gen_xor_i32(ret, arg1, arg2);
tcg_gen_not_i32(ret, ret); tcg_gen_not_i32(ret, ret);
@ -2279,8 +2279,8 @@ void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
if (TCG_TARGET_REG_BITS == 32) { if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
} else if (tcg_op_supported(INDEX_op_eqv_i64, TCG_TYPE_I64, 0)) { } else if (tcg_op_supported(INDEX_op_eqv, TCG_TYPE_I64, 0)) {
tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2); tcg_gen_op3_i64(INDEX_op_eqv, ret, arg1, arg2);
} else { } else {
tcg_gen_xor_i64(ret, arg1, arg2); tcg_gen_xor_i64(ret, arg1, arg2);
tcg_gen_not_i64(ret, ret); tcg_gen_not_i64(ret, ret);

6
tcg/tcg.c
View file

@ -1007,8 +1007,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_add, TCGOutOpBinary, outop_add), OUTOP(INDEX_op_add, TCGOutOpBinary, outop_add),
OUTOP(INDEX_op_and, TCGOutOpBinary, outop_and), OUTOP(INDEX_op_and, TCGOutOpBinary, outop_and),
OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc), OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc),
OUTOP(INDEX_op_eqv_i32, TCGOutOpBinary, outop_eqv), OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv),
OUTOP(INDEX_op_eqv_i64, TCGOutOpBinary, outop_eqv),
OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or), OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or),
OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc), OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc),
OUTOP(INDEX_op_xor, TCGOutOpBinary, outop_xor), OUTOP(INDEX_op_xor, TCGOutOpBinary, outop_xor),
@ -5436,8 +5435,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
case INDEX_op_add: case INDEX_op_add:
case INDEX_op_and: case INDEX_op_and:
case INDEX_op_andc: case INDEX_op_andc:
case INDEX_op_eqv_i32: case INDEX_op_eqv:
case INDEX_op_eqv_i64:
case INDEX_op_or: case INDEX_op_or:
case INDEX_op_orc: case INDEX_op_orc:
case INDEX_op_xor: case INDEX_op_xor:

5
tcg/tci.c
View file

@ -555,7 +555,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrr(insn, &r0, &r1, &r2); tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] | ~regs[r2]; regs[r0] = regs[r1] | ~regs[r2];
break; break;
CASE_32_64(eqv) case INDEX_op_eqv:
tci_args_rrr(insn, &r0, &r1, &r2); tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = ~(regs[r1] ^ regs[r2]); regs[r0] = ~(regs[r1] ^ regs[r2]);
break; break;
@ -1079,6 +1079,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_add: case INDEX_op_add:
case INDEX_op_and: case INDEX_op_and:
case INDEX_op_andc: case INDEX_op_andc:
case INDEX_op_eqv:
case INDEX_op_or: case INDEX_op_or:
case INDEX_op_orc: case INDEX_op_orc:
case INDEX_op_xor: case INDEX_op_xor:
@ -1086,8 +1087,6 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_sub_i64: case INDEX_op_sub_i64:
case INDEX_op_mul_i32: case INDEX_op_mul_i32:
case INDEX_op_mul_i64: case INDEX_op_mul_i64:
case INDEX_op_eqv_i32:
case INDEX_op_eqv_i64:
case INDEX_op_nand_i32: case INDEX_op_nand_i32:
case INDEX_op_nand_i64: case INDEX_op_nand_i64:
case INDEX_op_nor_i32: case INDEX_op_nor_i32:

2
tcg/tci/tcg-target.c.inc
View file

@ -663,7 +663,7 @@ static const TCGOutOpBinary outop_andc = {
static void tgen_eqv(TCGContext *s, TCGType type, static void tgen_eqv(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2) TCGReg a0, TCGReg a1, TCGReg a2)
{ {
tcg_out_op_rrr(s, glue(INDEX_op_eqv_i,TCG_TARGET_REG_BITS), a0, a1, a2); tcg_out_op_rrr(s, INDEX_op_eqv, a0, a1, a2);
} }
static const TCGOutOpBinary outop_eqv = { static const TCGOutOpBinary outop_eqv = {