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hw/misc/mps2-scc: Support using CFG0 bit 0 for remapping

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On some boards, SCC config register CFG0 bit 0 controls whether
parts of the board memory map are remapped. Support this with:
 * a device property scc-cfg0 so the board can specify the
   initial value of the CFG0 register
 * an outbound GPIO line which tracks bit 0 and which the board
   can wire up to provide the remapping

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210504120912.23094-3-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2021-05-04 13:09:11 +01:00
parent c52c266d24
commit 5bddf92e68
2 changed files with 19 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

9
include/hw/misc/mps2-scc.h
View file

@ -18,8 +18,14 @@
* + QOM property "scc-cfg4": value of the read-only CFG4 register
* + QOM property "scc-aid": value of the read-only SCC_AID register
* + QOM property "scc-id": value of the read-only SCC_ID register
* + QOM property "scc-cfg0": reset value of the CFG0 register
* + QOM property array "oscclk": reset values of the OSCCLK registers
* (which are accessed via the SYS_CFG channel provided by this device)
* + named GPIO output "remap": this tracks the value of CFG0 register
* bit 0. Boards where this bit controls memory remapping should
* connect this GPIO line to a function performing that mapping.
* Boards where bit 0 has no special function should leave the GPIO
* output disconnected.
*/
#ifndef MPS2_SCC_H
#define MPS2_SCC_H
@ -55,6 +61,9 @@ struct MPS2SCC {
uint32_t num_oscclk;
uint32_t *oscclk;
uint32_t *oscclk_reset;
uint32_t cfg0_reset;
qemu_irq remap;
};
#endif