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Use black code style for python scripts
Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Acked-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20230320092533.2859433-3-quic_mliebel@quicinc.com>
This commit is contained in:
Marco Liebel
Taylor Simpson
parent
cd6c4edff6
commit
5bb322e2a8
13 changed files with 1191 additions and 911 deletions
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@ -22,137 +22,141 @@ import re
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import string
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import hex_common
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##
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## Helpers for gen_analyze_func
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##
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def is_predicated(tag):
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return 'A_CONDEXEC' in hex_common.attribdict[tag]
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return "A_CONDEXEC" in hex_common.attribdict[tag]
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def analyze_opn_old(f, tag, regtype, regid, regno):
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regN = f"{regtype}{regid}N"
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predicated = "true" if is_predicated(tag) else "false"
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if (regtype == "R"):
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if (regid in {"ss", "tt"}):
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if regtype == "R":
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if regid in {"ss", "tt"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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elif (regid in {"dd", "ee", "xx", "yy"}):
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elif regid in {"dd", "ee", "xx", "yy"}:
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(f" ctx_log_reg_write_pair(ctx, {regN}, {predicated});\n")
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elif (regid in {"s", "t", "u", "v"}):
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elif regid in {"s", "t", "u", "v"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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elif (regid in {"d", "e", "x", "y"}):
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elif regid in {"d", "e", "x", "y"}:
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(f" ctx_log_reg_write(ctx, {regN}, {predicated});\n")
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else:
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "P"):
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if (regid in {"s", "t", "u", "v"}):
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elif regtype == "P":
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if regid in {"s", "t", "u", "v"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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elif (regid in {"d", "e", "x"}):
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elif regid in {"d", "e", "x"}:
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(f" ctx_log_pred_write(ctx, {regN});\n")
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else:
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "C"):
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if (regid == "ss"):
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f.write(f"// const int {regN} = insn->regno[{regno}] "
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"+ HEX_REG_SA0;\n")
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elif (regid == "dd"):
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f.write(f" const int {regN} = insn->regno[{regno}] "
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"+ HEX_REG_SA0;\n")
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elif regtype == "C":
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if regid == "ss":
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f.write(
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f"// const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n"
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)
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elif regid == "dd":
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f.write(f" const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n")
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f.write(f" ctx_log_reg_write_pair(ctx, {regN}, {predicated});\n")
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elif (regid == "s"):
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f.write(f"// const int {regN} = insn->regno[{regno}] "
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"+ HEX_REG_SA0;\n")
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elif (regid == "d"):
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f.write(f" const int {regN} = insn->regno[{regno}] "
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"+ HEX_REG_SA0;\n")
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elif regid == "s":
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f.write(
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f"// const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n"
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)
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elif regid == "d":
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f.write(f" const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n")
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f.write(f" ctx_log_reg_write(ctx, {regN}, {predicated});\n")
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else:
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "M"):
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if (regid == "u"):
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elif regtype == "M":
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if regid == "u":
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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else:
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "V"):
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elif regtype == "V":
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newv = "EXT_DFL"
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if (hex_common.is_new_result(tag)):
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if hex_common.is_new_result(tag):
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newv = "EXT_NEW"
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elif (hex_common.is_tmp_result(tag)):
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elif hex_common.is_tmp_result(tag):
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newv = "EXT_TMP"
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if (regid in {"dd", "xx"}):
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if regid in {"dd", "xx"}:
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(f" ctx_log_vreg_write_pair(ctx, {regN}, {newv}, "
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f"{predicated});\n")
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elif (regid in {"uu", "vv"}):
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f.write(
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f" ctx_log_vreg_write_pair(ctx, {regN}, {newv}, " f"{predicated});\n"
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)
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elif regid in {"uu", "vv"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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elif (regid in {"s", "u", "v", "w"}):
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elif regid in {"s", "u", "v", "w"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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elif (regid in {"d", "x", "y"}):
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elif regid in {"d", "x", "y"}:
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(f" ctx_log_vreg_write(ctx, {regN}, {newv}, "
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f"{predicated});\n")
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f.write(f" ctx_log_vreg_write(ctx, {regN}, {newv}, " f"{predicated});\n")
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else:
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "Q"):
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if (regid in {"d", "e", "x"}):
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elif regtype == "Q":
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if regid in {"d", "e", "x"}:
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(f" ctx_log_qreg_write(ctx, {regN});\n")
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elif (regid in {"s", "t", "u", "v"}):
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elif regid in {"s", "t", "u", "v"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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else:
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "G"):
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if (regid in {"dd"}):
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elif regtype == "G":
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if regid in {"dd"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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elif (regid in {"d"}):
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elif regid in {"d"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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elif (regid in {"ss"}):
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elif regid in {"ss"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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elif (regid in {"s"}):
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elif regid in {"s"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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else:
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "S"):
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if (regid in {"dd"}):
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elif regtype == "S":
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if regid in {"dd"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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elif (regid in {"d"}):
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elif regid in {"d"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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elif (regid in {"ss"}):
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elif regid in {"ss"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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elif (regid in {"s"}):
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elif regid in {"s"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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else:
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print("Bad register parse: ", regtype, regid)
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else:
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print("Bad register parse: ", regtype, regid)
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def analyze_opn_new(f, tag, regtype, regid, regno):
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regN = f"{regtype}{regid}N"
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if (regtype == "N"):
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if (regid in {"s", "t"}):
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if regtype == "N":
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if regid in {"s", "t"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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else:
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "P"):
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if (regid in {"t", "u", "v"}):
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elif regtype == "P":
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if regid in {"t", "u", "v"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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else:
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "O"):
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if (regid == "s"):
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elif regtype == "O":
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if regid == "s":
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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else:
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print("Bad register parse: ", regtype, regid)
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else:
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print("Bad register parse: ", regtype, regid)
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def analyze_opn(f, tag, regtype, regid, toss, numregs, i):
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if (hex_common.is_pair(regid)):
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if hex_common.is_pair(regid):
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analyze_opn_old(f, tag, regtype, regid, i)
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elif (hex_common.is_single(regid)):
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elif hex_common.is_single(regid):
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if hex_common.is_old_val(regtype, regid, tag):
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analyze_opn_old(f,tag, regtype, regid, i)
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analyze_opn_old(f, tag, regtype, regid, i)
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elif hex_common.is_new_val(regtype, regid, tag):
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analyze_opn_new(f, tag, regtype, regid, i)
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else:
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@ -160,6 +164,7 @@ def analyze_opn(f, tag, regtype, regid, toss, numregs, i):
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else:
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print("Bad register parse: ", regtype, regid, toss, numregs)
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##
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## Generate the code to analyze the instruction
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## For A2_add: Rd32=add(Rs32,Rt32), { RdV=RsV+RtV;}
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@ -175,24 +180,25 @@ def analyze_opn(f, tag, regtype, regid, toss, numregs, i):
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##
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def gen_analyze_func(f, tag, regs, imms):
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f.write(f"static void analyze_{tag}(DisasContext *ctx)\n")
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f.write('{\n')
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f.write("{\n")
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f.write(" Insn *insn G_GNUC_UNUSED = ctx->insn;\n")
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i=0
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i = 0
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## Analyze all the registers
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for regtype, regid, toss, numregs in regs:
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analyze_opn(f, tag, regtype, regid, toss, numregs, i)
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i += 1
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has_generated_helper = (not hex_common.skip_qemu_helper(tag) and
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not hex_common.is_idef_parser_enabled(tag))
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if (has_generated_helper and
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'A_SCALAR_LOAD' in hex_common.attribdict[tag]):
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has_generated_helper = not hex_common.skip_qemu_helper(
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tag
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) and not hex_common.is_idef_parser_enabled(tag)
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if has_generated_helper and "A_SCALAR_LOAD" in hex_common.attribdict[tag]:
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f.write(" ctx->need_pkt_has_store_s1 = true;\n")
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f.write("}\n\n")
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def main():
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hex_common.read_semantics_file(sys.argv[1])
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hex_common.read_attribs_file(sys.argv[2])
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@ -214,7 +220,7 @@ def main():
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tagregs = hex_common.get_tagregs()
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tagimms = hex_common.get_tagimms()
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with open(sys.argv[-1], 'w') as f:
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with open(sys.argv[-1], "w") as f:
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f.write("#ifndef HEXAGON_TCG_FUNCS_H\n")
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f.write("#define HEXAGON_TCG_FUNCS_H\n\n")
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@ -223,5 +229,6 @@ def main():
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f.write("#endif /* HEXAGON_TCG_FUNCS_H */\n")
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if __name__ == "__main__":
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main()
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