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target/arm: Handle AArch32 CP15 trapping via HSTR_EL2

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HSTR_EL2 offers a way to trap ranges of CP15 system register
accesses to EL2, and it looks like this register is completely
ignored by QEMU.

To avoid adding extra .accessfn filters all over the place (which
would have a direct performance impact), let's add a new TB flag
that gets set whenever HSTR_EL2 is non-zero and that QEMU translates
a context where this trap has a chance to apply, and only generate
the extra access check if the hypervisor is actively using this feature.

Tested with a hand-crafted KVM guest accessing CBAR.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191201122018.25808-5-maz@kernel.org
[PMM: use is_a64(); fix comment syntax]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Marc Zyngier 2019-12-01 12:20:17 +00:00 • committed by Peter Maydell
parent 9ca1d776cb
commit 5bb0a20b74
5 changed files with 34 additions and 1 deletions
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22
target/arm/op_helper.c
View file

@ -603,6 +603,27 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env));
}
/*
* Check for an EL2 trap due to HSTR_EL2. We expect EL0 accesses
* to sysregs non accessible at EL0 to have UNDEF-ed already.
*/
if (!is_a64(env) && arm_current_el(env) < 2 && ri->cp == 15 &&
(arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
uint32_t mask = 1 << ri->crn;
if (ri->type & ARM_CP_64BIT) {
mask = 1 << ri->crm;
}
/* T4 and T14 are RES0 */
mask &= ~((1 << 4) | (1 << 14));
if (env->cp15.hstr_el2 & mask) {
target_el = 2;
goto exept;
}
}
if (!ri->accessfn) {
return;
}
@ -652,6 +673,7 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
g_assert_not_reached();
}
exept:
raise_exception(env, EXCP_UDEF, syndrome, target_el);
}