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target/xtensa: drop DisasContext::litbase

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It doesn't help much, always-set bit 0 of the LITBASE SR is easy to
compensate with decrement of the l32r immediate argument.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2017-02-20 10:41:45 -08:00
parent e55239e2b6
commit 5b9b27639e
1 changed files with 5 additions and 22 deletions
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27
target/xtensa/translate.c
View file

@ -59,7 +59,6 @@ typedef struct DisasContext {
int ring; int ring;
uint32_t lbeg; uint32_t lbeg;
uint32_t lend; uint32_t lend;
TCGv_i32 litbase;
int is_jmp; int is_jmp;
int singlestep_enabled; int singlestep_enabled;
@ -261,21 +260,6 @@ static inline bool option_enabled(DisasContext *dc, int opt)
return xtensa_option_enabled(dc->config, opt); return xtensa_option_enabled(dc->config, opt);
} }
static void init_litbase(DisasContext *dc)
{
if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
dc->litbase = tcg_temp_local_new_i32();
tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
}
}
static void reset_litbase(DisasContext *dc)
{
if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
tcg_temp_free(dc->litbase);
}
}
static void init_sar_tracker(DisasContext *dc) static void init_sar_tracker(DisasContext *dc)
{ {
dc->sar_5bit = false; dc->sar_5bit = false;
@ -1089,7 +1073,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
dc.slotbuf = xtensa_insnbuf_alloc(dc.config->isa); dc.slotbuf = xtensa_insnbuf_alloc(dc.config->isa);
} }
init_litbase(&dc);
init_sar_tracker(&dc); init_sar_tracker(&dc);
if (dc.icount) { if (dc.icount) {
dc.next_icount = tcg_temp_local_new_i32(); dc.next_icount = tcg_temp_local_new_i32();
@ -1164,7 +1147,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
dc.pc + xtensa_insn_len(env, &dc) <= next_page_start && dc.pc + xtensa_insn_len(env, &dc) <= next_page_start &&
!tcg_op_buf_full()); !tcg_op_buf_full());
done: done:
reset_litbase(&dc);
reset_sar_tracker(&dc); reset_sar_tracker(&dc);
if (dc.icount) { if (dc.icount) {
tcg_temp_free(dc.next_icount); tcg_temp_free(dc.next_icount);
@ -1667,12 +1649,13 @@ static void translate_l32r(DisasContext *dc, const uint32_t arg[],
const uint32_t par[]) const uint32_t par[])
{ {
if (gen_window_check1(dc, arg[0])) { if (gen_window_check1(dc, arg[0])) {
TCGv_i32 tmp = (dc->tb->flags & XTENSA_TBFLAG_LITBASE) ? TCGv_i32 tmp;
tcg_const_i32(dc->raw_arg[1] - 1) :
tcg_const_i32(arg[1]);
if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
tcg_gen_add_i32(tmp, tmp, dc->litbase); tmp = tcg_const_i32(dc->raw_arg[1] - 1);
tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp);
} else {
tmp = tcg_const_i32(arg[1]);
} }
tcg_gen_qemu_ld32u(cpu_R[arg[0]], tmp, dc->cring); tcg_gen_qemu_ld32u(cpu_R[arg[0]], tmp, dc->cring);
tcg_temp_free(tmp); tcg_temp_free(tmp);