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Revert "hw/char/pl011: Warn when using disabled receiver"

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The guest does not control whether characters are sent on the UART.
Sending them before the guest happens to boot will now result in a
"guest error" log entry that is only because of timing, even if the
guest _would_ later setup the receiver correctly.

This reverts the bulk of commit abf2b6a028,
and instead adds a comment about why we don't check the enable bits.

Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 20250311153717.206129-1-pbonzini@redhat.com
[PMM: expanded comment]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Paolo Bonzini 2025-03-11 16:37:17 +01:00 • committed by Peter Maydell
parent 9223d68811
commit 5b14454d37
1 changed files with 10 additions and 9 deletions
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19
hw/char/pl011.c
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@ -490,16 +490,17 @@ static int pl011_can_receive(void *opaque)
unsigned fifo_depth = pl011_get_fifo_depth(s);
unsigned fifo_available = fifo_depth - s->read_count;
if (!(s->cr & CR_UARTEN)) {
qemu_log_mask(LOG_GUEST_ERROR,
"PL011 receiving data on disabled UART\n");
}
if (!(s->cr & CR_RXE)) {
qemu_log_mask(LOG_GUEST_ERROR,
"PL011 receiving data on disabled RX UART\n");
}
trace_pl011_can_receive(s->lcr, s->read_count, fifo_depth, fifo_available);
/*
* In theory we should check the UART and RX enable bits here and
* return 0 if they are not set (so the guest can't receive data
* until you have enabled the UART). In practice we suspect there
* is at least some guest code out there which has been tested only
* on QEMU and which never bothers to enable the UART because we
* historically never enforced that. So we effectively keep the
* UART continuously enabled regardless of the enable bits.
*/
trace_pl011_can_receive(s->lcr, s->read_count, fifo_depth, fifo_available);
return fifo_available;
}