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target/microblaze: Split out FSR from env->sregs
Continue eliminating the sregs array in favor of individual members. Does not correct the width of FSR, yet. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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5 changed files with 13 additions and 10 deletions
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@ -96,10 +96,10 @@ void cpu_loop(CPUMBState *env)
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case ESR_EC_FPU:
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info.si_signo = TARGET_SIGFPE;
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info.si_errno = 0;
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if (env->sregs[SR_FSR] & FSR_IO) {
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if (env->fsr & FSR_IO) {
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info.si_code = TARGET_FPE_FLTINV;
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}
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if (env->sregs[SR_FSR] & FSR_DZ) {
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if (env->fsr & FSR_DZ) {
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info.si_code = TARGET_FPE_FLTDIV;
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}
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info._sifields._sigfault._addr = 0;
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