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hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device

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Connect the Cadence GEM ethernet device. This also requires us to
expose the plic interrupt lines.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
This commit is contained in:
Alistair Francis 2018-04-26 13:59:08 -07:00
parent bde3ab9a9f
commit 5a7f76a3d4
4 changed files with 61 additions and 2 deletions
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9
include/hw/riscv/sifive_u.h
View file

@ -19,6 +19,8 @@
#ifndef HW_SIFIVE_U_H
#define HW_SIFIVE_U_H
#include "hw/net/cadence_gem.h"
#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
#define RISCV_U_SOC(obj) \
OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC)
@ -30,6 +32,7 @@ typedef struct SiFiveUSoCState {
/*< public >*/
RISCVHartArrayState cpus;
DeviceState *plic;
CadenceGEMState gem;
} SiFiveUSoCState;
typedef struct SiFiveUState {
@ -49,12 +52,14 @@ enum {
SIFIVE_U_PLIC,
SIFIVE_U_UART0,
SIFIVE_U_UART1,
SIFIVE_U_DRAM
SIFIVE_U_DRAM,
SIFIVE_U_GEM
};
enum {
SIFIVE_U_UART0_IRQ = 3,
SIFIVE_U_UART1_IRQ = 4
SIFIVE_U_UART1_IRQ = 4,
SIFIVE_U_GEM_IRQ = 0x35
};
enum {