tcg/tci: Split out tci_args_rrcl and tci_args_rrrrcl

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-01-29 21:41:13 -10:00
parent 817cadd6ee
commit 5a0adf3490

View file

@ -214,6 +214,15 @@ static void tci_args_rrs(const uint8_t **tb_ptr,
*i2 = tci_read_s32(tb_ptr); *i2 = tci_read_s32(tb_ptr);
} }
static void tci_args_rrcl(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3)
{
*r0 = tci_read_r(tb_ptr);
*r1 = tci_read_r(tb_ptr);
*c2 = tci_read_b(tb_ptr);
*l3 = (void *)tci_read_label(tb_ptr);
}
static void tci_args_rrrc(const uint8_t **tb_ptr, static void tci_args_rrrc(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3)
{ {
@ -224,6 +233,17 @@ static void tci_args_rrrc(const uint8_t **tb_ptr,
} }
#if TCG_TARGET_REG_BITS == 32 #if TCG_TARGET_REG_BITS == 32
static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5)
{
*r0 = tci_read_r(tb_ptr);
*r1 = tci_read_r(tb_ptr);
*r2 = tci_read_r(tb_ptr);
*r3 = tci_read_r(tb_ptr);
*c4 = tci_read_b(tb_ptr);
*l5 = (void *)tci_read_label(tb_ptr);
}
static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5) TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5)
{ {
@ -390,7 +410,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tcg_target_ulong t0; tcg_target_ulong t0;
tcg_target_ulong t1; tcg_target_ulong t1;
tcg_target_ulong t2; tcg_target_ulong t2;
tcg_target_ulong label;
TCGCond condition; TCGCond condition;
target_ulong taddr; target_ulong taddr;
uint8_t tmp8; uint8_t tmp8;
@ -399,7 +418,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
uint64_t tmp64; uint64_t tmp64;
#if TCG_TARGET_REG_BITS == 32 #if TCG_TARGET_REG_BITS == 32
TCGReg r3, r4; TCGReg r3, r4;
uint64_t v64, T1, T2; uint64_t T1, T2;
#endif #endif
TCGMemOpIdx oi; TCGMemOpIdx oi;
int32_t ofs; int32_t ofs;
@ -596,13 +615,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break; break;
#endif #endif
case INDEX_op_brcond_i32: case INDEX_op_brcond_i32:
t0 = tci_read_rval(regs, &tb_ptr); tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr);
t1 = tci_read_rval(regs, &tb_ptr); if (tci_compare32(regs[r0], regs[r1], condition)) {
condition = *tb_ptr++;
label = tci_read_label(&tb_ptr);
if (tci_compare32(t0, t1, condition)) {
tci_assert(tb_ptr == old_code_ptr + op_size); tci_assert(tb_ptr == old_code_ptr + op_size);
tb_ptr = (uint8_t *)label; tb_ptr = ptr;
continue; continue;
} }
break; break;
@ -622,13 +638,12 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_write_reg64(regs, t1, t0, tmp64); tci_write_reg64(regs, t1, t0, tmp64);
break; break;
case INDEX_op_brcond2_i32: case INDEX_op_brcond2_i32:
tmp64 = tci_read_r64(regs, &tb_ptr); tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr);
v64 = tci_read_r64(regs, &tb_ptr); T1 = tci_uint64(regs[r1], regs[r0]);
condition = *tb_ptr++; T2 = tci_uint64(regs[r3], regs[r2]);
label = tci_read_label(&tb_ptr); if (tci_compare64(T1, T2, condition)) {
if (tci_compare64(tmp64, v64, condition)) {
tci_assert(tb_ptr == old_code_ptr + op_size); tci_assert(tb_ptr == old_code_ptr + op_size);
tb_ptr = (uint8_t *)label; tb_ptr = ptr;
continue; continue;
} }
break; break;
@ -768,13 +783,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break; break;
#endif #endif
case INDEX_op_brcond_i64: case INDEX_op_brcond_i64:
t0 = tci_read_rval(regs, &tb_ptr); tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr);
t1 = tci_read_rval(regs, &tb_ptr); if (tci_compare64(regs[r0], regs[r1], condition)) {
condition = *tb_ptr++;
label = tci_read_label(&tb_ptr);
if (tci_compare64(t0, t1, condition)) {
tci_assert(tb_ptr == old_code_ptr + op_size); tci_assert(tb_ptr == old_code_ptr + op_size);
tb_ptr = (uint8_t *)label; tb_ptr = ptr;
continue; continue;
} }
break; break;