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net: cadence_gem: clear RX control descriptor

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The RX ring descriptors control field is used for setting
SOF and EOF (start of frame and end of frame).
The SOF and EOF weren't cleared from the previous descriptors,
causing inconsistencies in ring buffer.
Fix that by clearing the control field of every descriptors we're
processing.

Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20200418085145.489726-1-rfried.dev@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Ramon Fried 2020-04-18 11:51:45 +03:00 • committed by Peter Maydell
parent f1e7cb1388
commit 59ab136a9e
1 changed files with 7 additions and 0 deletions
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7
hw/net/cadence_gem.c
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@ -411,6 +411,11 @@ static inline void rx_desc_set_sof(uint32_t *desc)
desc[1] |= DESC_1_RX_SOF;
}
static inline void rx_desc_clear_control(uint32_t *desc)
{
desc[1] = 0;
}
static inline void rx_desc_set_eof(uint32_t *desc)
{
desc[1] |= DESC_1_RX_EOF;
@ -999,6 +1004,8 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
rxbuf_ptr += MIN(bytes_to_copy, rxbufsize);
bytes_to_copy -= MIN(bytes_to_copy, rxbufsize);
rx_desc_clear_control(s->rx_desc[q]);
/* Update the descriptor. */
if (first_desc) {
rx_desc_set_sof(s->rx_desc[q]);