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target-mips: Implement FCR31's R/W bitmask and related functionalities
This patch implements read and write access rules for Mips floating point control and status register (FCR31). The change can be divided into following parts: - Add fields that will keep FCR31's R/W bitmask in procesor definitions and processor float_status structure. - Add appropriate value for FCR31's R/W bitmask for each supported processor. - Add function for setting snan_bit_is_one, and integrate it in appropriate places. - Modify handling of CTC1 (case 31) instruction to use FCR31's R/W bitmask. - Modify handling user mode executables for Mips, in relation to the bit EF_MIPS_NAN2008 from ELF header, that is in turn related to reading and writing to FCR31. - Modify gdb behavior in relation to FCR31. Signed-off-by: Thomas Schwinge <thomas@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Aleksandar Markovic
Leon Alrae
parent
87552089b6
commit
599bc5e89c
6 changed files with 56 additions and 19 deletions
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@ -84,6 +84,7 @@ struct mips_def_t {
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int32_t CP0_TCStatus_rw_bitmask;
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int32_t CP0_SRSCtl;
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int32_t CP1_fcr0;
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int32_t CP1_fcr31_rw_bitmask;
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int32_t CP1_fcr31;
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int32_t MSAIR;
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int32_t SEGBITS;
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@ -273,6 +274,8 @@ static const mips_def_t mips_defs[] =
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.CP0_Status_rw_bitmask = 0x3678FF1F,
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
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.CP1_fcr31 = 0,
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.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
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@ -303,6 +306,8 @@ static const mips_def_t mips_defs[] =
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(0xff << CP0TCSt_TASID),
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
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.CP1_fcr31 = 0,
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.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
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.CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
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.CP0_SRSConf0_rw_bitmask = 0x3fffffff,
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.CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
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@ -343,6 +348,8 @@ static const mips_def_t mips_defs[] =
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.CP0_Status_rw_bitmask = 0x3778FF1F,
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
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.CP1_fcr31 = 0,
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.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
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@ -427,6 +434,7 @@ static const mips_def_t mips_defs[] =
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(1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
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.CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
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.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
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.SEGBITS = 32,
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.PABITS = 40,
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.insn_flags = CPU_MIPS32R5 | ASE_MSA,
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@ -465,6 +473,7 @@ static const mips_def_t mips_defs[] =
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(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
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(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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.CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
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.CP1_fcr31_rw_bitmask = 0x0103FFFF,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
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@ -485,6 +494,8 @@ static const mips_def_t mips_defs[] =
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.CP0_Status_rw_bitmask = 0x3678FFFF,
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/* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
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.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
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.CP1_fcr31 = 0,
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.CP1_fcr31_rw_bitmask = 0x0183FFFF,
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.SEGBITS = 40,
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.PABITS = 36,
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.insn_flags = CPU_MIPS3,
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@ -503,6 +514,8 @@ static const mips_def_t mips_defs[] =
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.CP0_Status_rw_bitmask = 0x3678FFFF,
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/* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
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.CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
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.CP1_fcr31 = 0,
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.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
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.SEGBITS = 40,
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.PABITS = 32,
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.insn_flags = CPU_VR54XX,
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@ -548,6 +561,8 @@ static const mips_def_t mips_defs[] =
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/* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
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.CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
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(0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
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.CP1_fcr31 = 0,
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.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
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.SEGBITS = 42,
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.PABITS = 36,
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.insn_flags = CPU_MIPS64,
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@ -575,6 +590,8 @@ static const mips_def_t mips_defs[] =
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.CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
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(1 << FCR0_D) | (1 << FCR0_S) |
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(0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
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.CP1_fcr31 = 0,
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.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
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.SEGBITS = 40,
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.PABITS = 36,
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.insn_flags = CPU_MIPS64 | ASE_MIPS3D,
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@ -601,6 +618,8 @@ static const mips_def_t mips_defs[] =
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
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(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
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(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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.CP1_fcr31 = 0,
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.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
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.SEGBITS = 42,
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.PABITS = 36,
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.insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
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@ -686,6 +705,7 @@ static const mips_def_t mips_defs[] =
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(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
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(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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.CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
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.CP1_fcr31_rw_bitmask = 0x0103FFFF,
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.SEGBITS = 48,
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.PABITS = 48,
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.insn_flags = CPU_MIPS64R6 | ASE_MSA,
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@ -704,6 +724,8 @@ static const mips_def_t mips_defs[] =
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x35D0FFFF,
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.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
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.CP1_fcr31 = 0,
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.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
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.SEGBITS = 40,
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.PABITS = 40,
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.insn_flags = CPU_LOONGSON2E,
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@ -722,6 +744,8 @@ static const mips_def_t mips_defs[] =
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */
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.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
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.CP1_fcr31 = 0,
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.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
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.SEGBITS = 40,
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.PABITS = 40,
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.insn_flags = CPU_LOONGSON2F,
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@ -749,6 +773,8 @@ static const mips_def_t mips_defs[] =
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
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(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
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(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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.CP1_fcr31 = 0,
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.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
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.SEGBITS = 42,
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.PABITS = 36,
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.insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
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