mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-07 01:33:56 -06:00
target/riscv: Split gen_arith_imm into functional and temp
The tcg_gen_fooi_tl functions have some immediate constant folding built in, which match up with some of the riscv asm builtin macros, like mv and not. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
parent
0e68e240a9
commit
598aa1160c
2 changed files with 24 additions and 9 deletions
|
@ -223,7 +223,7 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a)
|
|||
|
||||
static bool trans_addi(DisasContext *ctx, arg_addi *a)
|
||||
{
|
||||
return gen_arith_imm(ctx, a, &tcg_gen_add_tl);
|
||||
return gen_arith_imm_fn(ctx, a, &tcg_gen_addi_tl);
|
||||
}
|
||||
|
||||
static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
|
||||
|
@ -239,25 +239,25 @@ static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
|
|||
|
||||
static bool trans_slti(DisasContext *ctx, arg_slti *a)
|
||||
{
|
||||
return gen_arith_imm(ctx, a, &gen_slt);
|
||||
return gen_arith_imm_tl(ctx, a, &gen_slt);
|
||||
}
|
||||
|
||||
static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
|
||||
{
|
||||
return gen_arith_imm(ctx, a, &gen_sltu);
|
||||
return gen_arith_imm_tl(ctx, a, &gen_sltu);
|
||||
}
|
||||
|
||||
static bool trans_xori(DisasContext *ctx, arg_xori *a)
|
||||
{
|
||||
return gen_arith_imm(ctx, a, &tcg_gen_xor_tl);
|
||||
return gen_arith_imm_fn(ctx, a, &tcg_gen_xori_tl);
|
||||
}
|
||||
static bool trans_ori(DisasContext *ctx, arg_ori *a)
|
||||
{
|
||||
return gen_arith_imm(ctx, a, &tcg_gen_or_tl);
|
||||
return gen_arith_imm_fn(ctx, a, &tcg_gen_ori_tl);
|
||||
}
|
||||
static bool trans_andi(DisasContext *ctx, arg_andi *a)
|
||||
{
|
||||
return gen_arith_imm(ctx, a, &tcg_gen_and_tl);
|
||||
return gen_arith_imm_fn(ctx, a, &tcg_gen_andi_tl);
|
||||
}
|
||||
static bool trans_slli(DisasContext *ctx, arg_slli *a)
|
||||
{
|
||||
|
@ -364,7 +364,7 @@ static bool trans_and(DisasContext *ctx, arg_and *a)
|
|||
#ifdef TARGET_RISCV64
|
||||
static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
|
||||
{
|
||||
return gen_arith_imm(ctx, a, &gen_addw);
|
||||
return gen_arith_imm_tl(ctx, a, &gen_addw);
|
||||
}
|
||||
|
||||
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue