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Fifth RISC-V PR for QEMU 7.0
* Fixup checks for ext_zb[abcs]
* Add AIA support for virt machine
* Increase maximum number of CPUs in virt machine
* Fixup OpenTitan SPI address
* Add support for zfinx, zdinx and zhinx{min} extensions
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Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20220303' into staging
Fifth RISC-V PR for QEMU 7.0
* Fixup checks for ext_zb[abcs]
* Add AIA support for virt machine
* Increase maximum number of CPUs in virt machine
* Fixup OpenTitan SPI address
* Add support for zfinx, zdinx and zhinx{min} extensions
# gpg: Signature made Thu 03 Mar 2022 05:26:55 GMT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20220303:
target/riscv: expose zfinx, zdinx, zhinx{min} properties
target/riscv: add support for zhinx/zhinxmin
target/riscv: add support for zdinx
target/riscv: add support for zfinx
target/riscv: hardwire mstatus.FS to zero when enable zfinx
target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
hw: riscv: opentitan: fixup SPI addresses
hw/riscv: virt: Increase maximum number of allowed CPUs
docs/system: riscv: Document AIA options for virt machine
hw/riscv: virt: Add optional AIA IMSIC support to virt machine
hw/intc: Add RISC-V AIA IMSIC device emulation
hw/riscv: virt: Add optional AIA APLIC support to virt machine
target/riscv: fix inverted checks for ext_zb[abcs]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
5959ef7d43
22 changed files with 2145 additions and 500 deletions
68
include/hw/intc/riscv_imsic.h
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68
include/hw/intc/riscv_imsic.h
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@ -0,0 +1,68 @@
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/*
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* RISC-V IMSIC (Incoming Message Signal Interrupt Controller) interface
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*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_RISCV_IMSIC_H
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#define HW_RISCV_IMSIC_H
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#define TYPE_RISCV_IMSIC "riscv.imsic"
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typedef struct RISCVIMSICState RISCVIMSICState;
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DECLARE_INSTANCE_CHECKER(RISCVIMSICState, RISCV_IMSIC, TYPE_RISCV_IMSIC)
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#define IMSIC_MMIO_PAGE_SHIFT 12
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#define IMSIC_MMIO_PAGE_SZ (1UL << IMSIC_MMIO_PAGE_SHIFT)
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#define IMSIC_MMIO_SIZE(__num_pages) ((__num_pages) * IMSIC_MMIO_PAGE_SZ)
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#define IMSIC_MMIO_HART_GUEST_MAX_BTIS 6
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#define IMSIC_MMIO_GROUP_MIN_SHIFT 24
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#define IMSIC_HART_NUM_GUESTS(__guest_bits) \
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(1U << (__guest_bits))
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#define IMSIC_HART_SIZE(__guest_bits) \
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(IMSIC_HART_NUM_GUESTS(__guest_bits) * IMSIC_MMIO_PAGE_SZ)
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#define IMSIC_GROUP_NUM_HARTS(__hart_bits) \
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(1U << (__hart_bits))
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#define IMSIC_GROUP_SIZE(__hart_bits, __guest_bits) \
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(IMSIC_GROUP_NUM_HARTS(__hart_bits) * IMSIC_HART_SIZE(__guest_bits))
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struct RISCVIMSICState {
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/*< private >*/
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SysBusDevice parent_obj;
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qemu_irq *external_irqs;
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/*< public >*/
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MemoryRegion mmio;
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uint32_t num_eistate;
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uint32_t *eidelivery;
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uint32_t *eithreshold;
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uint32_t *eistate;
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/* config */
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bool mmode;
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uint32_t hartid;
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uint32_t num_pages;
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uint32_t num_irqs;
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};
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DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode,
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uint32_t num_pages, uint32_t num_ids);
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#endif
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@ -57,8 +57,10 @@ enum {
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IBEX_DEV_FLASH,
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IBEX_DEV_FLASH_VIRTUAL,
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IBEX_DEV_UART,
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IBEX_DEV_SPI_DEVICE,
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IBEX_DEV_SPI_HOST0,
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IBEX_DEV_SPI_HOST1,
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IBEX_DEV_GPIO,
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IBEX_DEV_SPI,
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IBEX_DEV_I2C,
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IBEX_DEV_PATTGEN,
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IBEX_DEV_TIMER,
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@ -24,26 +24,36 @@
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#include "hw/block/flash.h"
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#include "qom/object.h"
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#define VIRT_CPUS_MAX 32
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#define VIRT_SOCKETS_MAX 8
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#define VIRT_CPUS_MAX_BITS 9
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#define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS)
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#define VIRT_SOCKETS_MAX_BITS 2
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#define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS)
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#define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
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typedef struct RISCVVirtState RISCVVirtState;
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DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE,
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TYPE_RISCV_VIRT_MACHINE)
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typedef enum RISCVVirtAIAType {
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VIRT_AIA_TYPE_NONE = 0,
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VIRT_AIA_TYPE_APLIC,
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VIRT_AIA_TYPE_APLIC_IMSIC,
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} RISCVVirtAIAType;
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struct RISCVVirtState {
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/*< private >*/
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MachineState parent;
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/*< public >*/
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RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
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DeviceState *plic[VIRT_SOCKETS_MAX];
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DeviceState *irqchip[VIRT_SOCKETS_MAX];
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PFlashCFI01 *flash[2];
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FWCfgState *fw_cfg;
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int fdt_size;
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bool have_aclint;
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RISCVVirtAIAType aia_type;
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int aia_guests;
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};
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enum {
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@ -54,9 +64,13 @@ enum {
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VIRT_CLINT,
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VIRT_ACLINT_SSWI,
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VIRT_PLIC,
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VIRT_APLIC_M,
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VIRT_APLIC_S,
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VIRT_UART0,
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VIRT_VIRTIO,
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VIRT_FW_CFG,
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VIRT_IMSIC_M,
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VIRT_IMSIC_S,
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VIRT_FLASH,
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VIRT_DRAM,
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VIRT_PCIE_MMIO,
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@ -73,8 +87,13 @@ enum {
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VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
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};
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#define VIRT_PLIC_NUM_SOURCES 127
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#define VIRT_PLIC_NUM_PRIORITIES 7
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#define VIRT_IRQCHIP_IPI_MSI 1
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#define VIRT_IRQCHIP_NUM_MSIS 255
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#define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV
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#define VIRT_IRQCHIP_NUM_PRIO_BITS 3
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#define VIRT_IRQCHIP_MAX_GUESTS_BITS 3
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#define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U)
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#define VIRT_PLIC_PRIORITY_BASE 0x04
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#define VIRT_PLIC_PENDING_BASE 0x1000
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#define VIRT_PLIC_ENABLE_BASE 0x2000
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@ -86,9 +105,15 @@ enum {
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#define FDT_PCI_ADDR_CELLS 3
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#define FDT_PCI_INT_CELLS 1
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#define FDT_PLIC_ADDR_CELLS 0
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#define FDT_PLIC_INT_CELLS 1
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#define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \
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FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS)
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#define FDT_APLIC_INT_CELLS 2
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#define FDT_IMSIC_INT_CELLS 0
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#define FDT_MAX_INT_CELLS 2
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#define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
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1 + FDT_MAX_INT_CELLS)
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#define FDT_PLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
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1 + FDT_PLIC_INT_CELLS)
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#define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
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1 + FDT_APLIC_INT_CELLS)
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#endif
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