motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-05 00:33:55 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/m68k: Implement atomic test-and-set

Browse source 
This is slightly more complicated than cas,
because tas is allowed on data registers.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20220829051746.227094-1-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
This commit is contained in:
Richard Henderson 2022-08-28 22:17:46 -07:00 • committed by Laurent Vivier
parent 832e9e33bc
commit 5934dae7a7
1 changed files with 30 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

40
target/m68k/translate.c
View file

@ -2825,19 +2825,39 @@ DISAS_INSN(illegal)
gen_exception(s, s->base.pc_next, EXCP_ILLEGAL); gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
} }
/* ??? This should be atomic. */
DISAS_INSN(tas) DISAS_INSN(tas)
{ {
TCGv dest; int mode = extract32(insn, 3, 3);
TCGv src1; int reg0 = REG(insn, 0);
TCGv addr;
dest = tcg_temp_new(); if (mode == 0) {
SRC_EA(env, src1, OS_BYTE, 1, &addr); /* data register direct */
gen_logic_cc(s, src1, OS_BYTE); TCGv dest = cpu_dregs[reg0];
tcg_gen_ori_i32(dest, src1, 0x80); gen_logic_cc(s, dest, OS_BYTE);
DEST_EA(env, insn, OS_BYTE, dest, &addr); tcg_gen_ori_tl(dest, dest, 0x80);
tcg_temp_free(dest); } else {
TCGv src1, addr;
addr = gen_lea_mode(env, s, mode, reg0, OS_BYTE);
if (IS_NULL_QREG(addr)) {
gen_addr_fault(s);
return;
}
src1 = tcg_temp_new();
tcg_gen_atomic_fetch_or_tl(src1, addr, tcg_constant_tl(0x80),
IS_USER(s), MO_SB);
gen_logic_cc(s, src1, OS_BYTE);
tcg_temp_free(src1);
switch (mode) {
case 3: /* Indirect postincrement. */
tcg_gen_addi_i32(AREG(insn, 0), addr, 1);
break;
case 4: /* Indirect predecrememnt. */
tcg_gen_mov_i32(AREG(insn, 0), addr);
break;
}
}
} }
DISAS_INSN(mull) DISAS_INSN(mull)