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MIPS atomic instructions

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Implement MIPS ll/sc instructions using atomic compare+exchange.

Signed-off-by: Paul Brook <paul@codesourcery.com>
This commit is contained in:
Paul Brook 2009-07-09 17:45:17 +01:00
parent ff867ddcbd
commit 590bc601d8
3 changed files with 124 additions and 24 deletions
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5
target-mips/cpu.h
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@ -375,6 +375,9 @@ struct CPUMIPSState {
int32_t CP0_Config7;
/* XXX: Maybe make LLAddr per-TC? */
target_ulong CP0_LLAddr;
target_ulong llval;
target_ulong llnewval;
target_ulong llreg;
target_ulong CP0_WatchLo[8];
int32_t CP0_WatchHi[8];
target_ulong CP0_XContext;
@ -559,6 +562,8 @@ enum {
EXCP_LAST = EXCP_CACHE,
};
/* Dummy exception for conditional stores. */
#define EXCP_SC 0x100
int cpu_mips_exec(CPUMIPSState *s);
CPUMIPSState *cpu_mips_init(const char *cpu_model);