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target/ppc: Move 1T segment and AMR options to PPCHash64Options

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Currently env->mmu_model is a bit of an unholy mess of an enum of distinct
MMU types, with various flag bits as well.  This makes which bits of the
field should be compared pretty confusing.

Make a start on cleaning that up by moving two of the flags bits -
POWERPC_MMU_1TSEG and POWERPC_MMU_AMR - which are specific to the 64-bit
hash MMU into a new flags field in PPCHash64Options structure.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
This commit is contained in:
David Gibson 2018-03-23 14:11:07 +11:00
parent 21e405f1ec
commit 58969eeece
6 changed files with 20 additions and 14 deletions
Download patch file Download diff file Expand all files Collapse all files

6
target/ppc/mmu-hash64.c
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@ -160,7 +160,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
return -1; /* Bad segment size */
}
if ((vsid & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
if ((vsid & SLB_VSID_B) && !(ppc_hash64_has(cpu, PPC_HASH64_1TSEG))) {
return -1; /* 1T segment on MMU that doesn't support it */
}
@ -369,7 +369,7 @@ static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte)
int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
/* Only recent MMUs implement Virtual Page Class Key Protection */
if (!(env->mmu_model & POWERPC_MMU_AMR)) {
if (!ppc_hash64_has(cpu, PPC_HASH64_AMR)) {
return prot;
}
@ -1114,6 +1114,7 @@ void ppc_hash64_finalize(PowerPCCPU *cpu)
}
const PPCHash64Options ppc_hash64_opts_basic = {
.flags = 0,
.sps = {
{ .page_shift = 12, /* 4K */
.slb_enc = 0,
@ -1127,6 +1128,7 @@ const PPCHash64Options ppc_hash64_opts_basic = {
};
const PPCHash64Options ppc_hash64_opts_POWER7 = {
.flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR,
.sps = {
{
.page_shift = 12, /* 4K */