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target/ppc: Split off common embedded TLB init

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Several 4xx CPUs and e200 share the same TLB settings enclosed in an
ifdef. Split it off in a common function to reduce code duplication
and the number of ifdefs.

Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
BALATON Zoltan 2024-05-13 01:28:03 +02:00 • committed by Nicholas Piggin
parent 5fd257f599
commit 581eea5d65
1 changed files with 17 additions and 29 deletions
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46
target/ppc/cpu_init.c
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@ -2127,18 +2127,22 @@ static int check_attn_hid0_power9(CPUPPCState *env)
} }
#endif #endif
static void init_tlbs_emb(CPUPPCState *env)
{
#ifndef CONFIG_USER_ONLY
env->nb_tlb = 64;
env->nb_ways = 1;
env->tlb_type = TLB_EMB;
#endif
}
static void init_proc_405(CPUPPCState *env) static void init_proc_405(CPUPPCState *env)
{ {
register_40x_sprs(env); register_40x_sprs(env);
register_405_sprs(env); register_405_sprs(env);
register_usprgh_sprs(env); register_usprgh_sprs(env);
/* Memory management */ init_tlbs_emb(env);
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
env->nb_ways = 1;
env->tlb_type = TLB_EMB;
#endif
init_excp_4xx(env); init_excp_4xx(env);
env->dcache_line_size = 32; env->dcache_line_size = 32;
env->icache_line_size = 32; env->icache_line_size = 32;
@ -2206,12 +2210,8 @@ static void init_proc_440EP(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic, &spr_read_generic, &spr_write_generic,
0x00000000); 0x00000000);
/* Memory management */
#if !defined(CONFIG_USER_ONLY) init_tlbs_emb(env);
env->nb_tlb = 64;
env->nb_ways = 1;
env->tlb_type = TLB_EMB;
#endif
init_excp_BookE(env); init_excp_BookE(env);
env->dcache_line_size = 32; env->dcache_line_size = 32;
env->icache_line_size = 32; env->icache_line_size = 32;
@ -2305,12 +2305,7 @@ static void init_proc_440GP(CPUPPCState *env)
register_440_sprs(env); register_440_sprs(env);
register_usprgh_sprs(env); register_usprgh_sprs(env);
/* Memory management */ init_tlbs_emb(env);
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
env->nb_ways = 1;
env->tlb_type = TLB_EMB;
#endif
init_excp_BookE(env); init_excp_BookE(env);
env->dcache_line_size = 32; env->dcache_line_size = 32;
env->icache_line_size = 32; env->icache_line_size = 32;
@ -2379,12 +2374,8 @@ static void init_proc_440x5(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic, &spr_read_generic, &spr_write_generic,
0x00000000); 0x00000000);
/* Memory management */
#if !defined(CONFIG_USER_ONLY) init_tlbs_emb(env);
env->nb_tlb = 64;
env->nb_ways = 1;
env->tlb_type = TLB_EMB;
#endif
init_excp_BookE(env); init_excp_BookE(env);
env->dcache_line_size = 32; env->dcache_line_size = 32;
env->icache_line_size = 32; env->icache_line_size = 32;
@ -2747,11 +2738,8 @@ static void init_proc_e200(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic, &spr_read_generic, &spr_write_generic,
0x00000000); 0x00000000);
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64; init_tlbs_emb(env);
env->nb_ways = 1;
env->tlb_type = TLB_EMB;
#endif
init_excp_e200(env, 0xFFFF0000UL); init_excp_e200(env, 0xFFFF0000UL);
env->dcache_line_size = 32; env->dcache_line_size = 32;
env->icache_line_size = 32; env->icache_line_size = 32;